From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7939) id 4A0533858D39; Wed, 21 Feb 2024 22:10:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4A0533858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1708553402; bh=l7YiKKFgrqIPQOCwXKgJJymOycvukbCazwdkJ1u0LMA=; h=From:To:Subject:Date:From; b=eyxPT7Ppvz1xp2l+USGKYvkIoh7y3vBjwZdzXBJ2ozWZhuHZAKZ/qKfQt3fKfzobL EzRixmXKb0JVab+Oxqm6+otrxW+TqzK6+MnKMJc1FyAkV33zsDLl08KxED5dMnytbO neiqDkV8WgeIBRA3eMDe2HSXgGpqb4mIQhZLxV8Y= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Edwin Lu To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-9123] RISC-V: Quick and simple fixes to testcases that break due to reordering X-Act-Checkin: gcc X-Git-Author: Edwin Lu X-Git-Refname: refs/heads/master X-Git-Oldrev: 67a29f99cc81384b9245ac5997e47bcf3ff84545 X-Git-Newrev: bc6b42666cfe1467774b942c7afabe480e3b5ccb Message-Id: <20240221221002.4A0533858D39@sourceware.org> Date: Wed, 21 Feb 2024 22:10:02 +0000 (GMT) List-Id: https://gcc.gnu.org/g:bc6b42666cfe1467774b942c7afabe480e3b5ccb commit r14-9123-gbc6b42666cfe1467774b942c7afabe480e3b5ccb Author: Edwin Lu Date: Wed Feb 14 12:06:38 2024 -0800 RISC-V: Quick and simple fixes to testcases that break due to reordering The following test cases are easily fixed with small updates to the expected assembly order. Additionally make calling-convention testcases more robust PR target/113249 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Rearrange and adjust asm-checker times * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Rearrange assembly * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl Signed-off-by: Edwin Lu Diff: --- .../riscv/rvv/autovec/vls/calling-convention-1.c | 27 +++++++++++++++++++--- .../riscv/rvv/autovec/vls/calling-convention-2.c | 23 ++++++++++++++++-- .../riscv/rvv/autovec/vls/calling-convention-3.c | 18 ++++++++++++++- .../riscv/rvv/autovec/vls/calling-convention-4.c | 12 +++++++++- .../riscv/rvv/autovec/vls/calling-convention-5.c | 22 +++++++++++++++++- .../riscv/rvv/autovec/vls/calling-convention-6.c | 17 ++++++++++++++ .../riscv/rvv/autovec/vls/calling-convention-7.c | 12 +++++++++- .../riscv/rvv/base/binop_vx_constraint-12.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-16.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-17.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-19.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-21.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-23.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-25.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-27.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-29.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-31.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-33.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-35.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-4.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-40.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-44.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-8.c | 4 +--- .../riscv/rvv/base/shift_vx_constraint-1.c | 5 +--- .../gcc.target/riscv/rvv/vsetvl/avl_single-107.c | 2 +- 25 files changed, 140 insertions(+), 62 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c index 41e31c258f8b..217885c2d67a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c @@ -143,12 +143,33 @@ DEF_RET1_ARG9 (v1024qi) DEF_RET1_ARG9 (v2048qi) DEF_RET1_ARG9 (v4096qi) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 9 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1qi tests: return value (lbu) and function prologue (sb) +// 1 lbu per test, argnum sb's when args > 1 /* { dg-final { scan-assembler-times {lbu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 35 } } */ /* { dg-final { scan-assembler-times {sb\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2qi test: return value (lhu) and function prologue (sh) +// 1 lhu per test, argnum sh's when args > 1 +/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v4qi tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 +/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v8qi and v16qi tests: return value (ld) and function prologue (sd) +// - 1 ld per v8qi and 2 ld per v16qi with args > 1 +// - 2 * argnum sd's per v8qi and 3 * argnum sd's per v16qi when argnum > 1 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v32-4096qi tests: return value (vse8.v) +/* { dg-final { scan-assembler-times {vse8.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// v1024-4096qi_ARG1 tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse8 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c index 8544f160e937..f45e6a74c886 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c @@ -133,10 +133,29 @@ DEF_RET1_ARG9 (v512hi) DEF_RET1_ARG9 (v1024hi) DEF_RET1_ARG9 (v2048hi) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1hi tests: return value (lhu) and function prologue (sh) +// 1 lhu per test, argnum sh's when args > 1 /* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 33 } } */ /* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2hi tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 +/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v4hi and v8hi tests: return value (ld) and function prologue (sd) +// - 1 ld per v4hi and 2 ld per v8hi with args > 1 +// - argnum sd's per v4hi when argnum > 1 +// - 2 * argnum sd's per v8hi when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v16-2048hi tests: return value (vse16.v) +/* { dg-final { scan-assembler-times {vse16.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// v512-2048qi_ARG1 tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse16 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c index 17b06933c729..6716b0aa413e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c @@ -123,8 +123,24 @@ DEF_RET1_ARG9 (v256si) DEF_RET1_ARG9 (v512si) DEF_RET1_ARG9 (v1024si) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1si tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 /* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 31 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2si and v4si tests: return value (ld) and function prologue (sd) +// - 1 ld per v2si and 2 ld per v4si with args > 1 +// - argnum sd's per v2si when argnum > 1 +// - 2 * argnum sd's per v4si when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v8-1024si tests: return value (vse32.v) +/* { dg-final { scan-assembler-times {vse32.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// 256-1024si tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse32 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c index 8c3f6ba98e32..0a649acea9ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c @@ -113,6 +113,16 @@ DEF_RET1_ARG9 (v128di) DEF_RET1_ARG9 (v256di) DEF_RET1_ARG9 (v512di) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 29 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1di and v2di tests: return value (ld) and function prologue (sd) +// - 1 ld per v1di and 2 ld per v2di with args > 1 +// - argnum sd's per v1di when argnum > 1 +// - 2 * argnum sd's per v2di when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v4-512di tests: return value (vse64.v) +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)} 77 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c index a0208d8f42bf..fd5146f5e6b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c @@ -133,9 +133,29 @@ DEF_RET1_ARG9 (v512hf) DEF_RET1_ARG9 (v1024hf) DEF_RET1_ARG9 (v2048hf) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1hf tests: return value (lhu) and function prologue (sh) +// 1 lhu per test, argnum sh's when args > 1 /* { dg-final { scan-assembler-times {lhu\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2hf tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 +/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v4hf and v8hf tests: return value (ld) and function prologue (sd) +// - 1 ld per v4hf and 2 ld per v8hf with args > 1 +// - argnum sd's per v4hf when argnum > 1 +// - 2 * argnum sd's per v8hf when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v16-2048hf tests: return value (vse16.v) +/* { dg-final { scan-assembler-times {vse16.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// v512-2048qf_ARG1 tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse16 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c index 58ef8bf65f3f..4723312ec09f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c @@ -123,7 +123,24 @@ DEF_RET1_ARG9 (v256sf) DEF_RET1_ARG9 (v512sf) DEF_RET1_ARG9 (v1024sf) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1sf tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 /* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2sf and v4sf tests: return value (ld) and function prologue (sd) +// - 1 ld per v2sf and 2 ld per v4sf with args > 1 +// - argnum sd's per v2sf when argnum > 1 +// - 2 * argnum sd's per v4sf when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v8-1024sf tests: return value (vse32.v) +/* { dg-final { scan-assembler-times {vse32.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// 256-1024sf tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse32 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c index e35ccd52e516..40e1b93bf55d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c @@ -113,6 +113,16 @@ DEF_RET1_ARG9 (v128df) DEF_RET1_ARG9 (v256df) DEF_RET1_ARG9 (v512df) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 29 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1df and v2df tests: return value (ld) and function prologue (sd) +// - 1 ld per v1df and 2 ld per v2df with args > 1 +// - argnum sd's per v1df when argnum > 1 +// - 2 * argnum sd's per v2df when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v4-512df tests: return value (vse64.v) +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)} 77 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c index 173ac625ada5..9a3327cde23d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c index 1edba8980b46..e83187dd1d3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c index 75340c3da6c9..9321b8f474d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c index 7e4aedc1cdc8..9a64c133dbc3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c index 755e92a9cd71..93249b2c92de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c index 2c82dc0688a9..0d6cb4ffca01 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c index e2ac6a3d9e1b..228359df2d6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c index 436a0e85f3d3..1960afbc2ee0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c index 72b321607c33..6d2c07403fd9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c index 72b321607c33..6d2c07403fd9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c index 6908c78e19b2..4b2a6c03f424 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c index 6908c78e19b2..4b2a6c03f424 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c index ee1db1c41aed..cebe6a61fe51 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c index fb969eb50a27..4379310f4799 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c index 542f43eca49f..806d9db46af6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c index 6a26248096dd..83d50711540b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c index 9e0b41ccba70..622c890d71b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -28,9 +26,8 @@ void f1 (void * in, void *out) ** f2: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... -** ... ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... ** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vsll\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t ** vse32.v\tv[0-9]+,0\([a-x0-9]+\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c index 2b5e9f778d7f..7b8acc25399c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c @@ -38,4 +38,4 @@ foo (int vl, int n, int m, int32_t *in, int32_t *out) } /* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ -/* { dg-final { scan-assembler-times {vsetvli\tzero,zero,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\tzero,a0,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */