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From: Pan Li <panli@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-9128] RISC-V: Upgrade RVV intrinsic version to 0.12 Date: Thu, 22 Feb 2024 01:23:37 +0000 (GMT) [thread overview] Message-ID: <20240222012337.16562385842A@sourceware.org> (raw) https://gcc.gnu.org/g:3688c2b1a604a16b9ff46935770976960016b15c commit r14-9128-g3688c2b1a604a16b9ff46935770976960016b15c Author: Pan Li <pan2.li@intel.com> Date: Wed Feb 21 12:06:22 2024 +0800 RISC-V: Upgrade RVV intrinsic version to 0.12 Upgrade the version of RVV intrinsic from 0.11 to 0.12. PR target/114017 gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade the version to 0.12. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the version to 0.12. * gcc.target/riscv/rvv/base/pr114017-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com> Diff: --- gcc/config/riscv/riscv-c.cc | 2 +- .../gcc.target/riscv/predef-__riscv_v_intrinsic.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 3ef06dcfd2d2..3755ec0b8ef3 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -139,7 +139,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) { builtin_define ("__riscv_vector"); builtin_define_with_int_value ("__riscv_v_intrinsic", - riscv_ext_version_value (0, 11)); + riscv_ext_version_value (0, 12)); } if (TARGET_XTHEADVECTOR) diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c index dbbedf54f878..07f1f159a8ff 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c @@ -3,7 +3,7 @@ int main () { -#if __riscv_v_intrinsic != 11000 +#if __riscv_v_intrinsic != 12000 #error "__riscv_v_intrinsic" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c new file mode 100644 index 000000000000..8eee7c68f71c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +vuint8mf2_t +test (vuint16m1_t val, size_t shift, size_t vl) +{ +#if __riscv_v_intrinsic == 11000 + #warning "RVV Intrinsics v0.11" + return __riscv_vnclipu (val, shift, vl); +#endif + +#if __riscv_v_intrinsic == 12000 + #warning "RVV Intrinsics v0.12" /* { dg-warning "RVV Intrinsics v0.12" } */ + return __riscv_vnclipu (val, shift, 0, vl); +#endif +} +
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