From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id EE3ED3858C52; Thu, 22 Feb 2024 20:38:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EE3ED3858C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1708634293; bh=MWLrT26EVTT2GxzSwyObMOkfJtuGdPicqE0zKJSbNLA=; h=From:To:Subject:Date:From; b=aKf1FHFVqtVyVf6niGP9xmTvcpz5IoQkz3hLMFD60RFAA3OoqW+9AresZHd3tFMsT ugJFTuYsgH8ixUYIManPfKQC8A3boPKmu1DMl60WEp9YQAH3jp2shySzfB6vQpgHv2 ByitcwR0hdGOD8kUNDNkl/YcpcnqxSgUUHJAoOhI= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work159)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work159 X-Git-Oldrev: 4e61dcc2db89cd0b2b5d85e29e0a561e50a59cf3 X-Git-Newrev: 160393278a3917a2b5d29bd2c73b5aa8c42f3de4 Message-Id: <20240222203813.EE3ED3858C52@sourceware.org> Date: Thu, 22 Feb 2024 20:38:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:160393278a3917a2b5d29bd2c73b5aa8c42f3de4 commit 160393278a3917a2b5d29bd2c73b5aa8c42f3de4 Author: Michael Meissner Date: Thu Feb 22 15:38:09 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 135 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 9fa3164d9dd2..4b75d2ae58ef 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,5 +1,140 @@ +==================== Branch work159, patch #3 ==================== + +Use vector pair load/store for memcpy with -mcpu=future + +In the development for the power10 processor, GCC did not enable using the load +vector pair and store vector pair instructions when optimizing things like +memory copy. This patch enables using those instructions if -mcpu=future is +used. + +2024-02-21 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using + load vector pair and store vector pair instructions for memory copy + operations. + (POWERPC_MASKS): Make the bit for enabling using load vector pair and + store vector pair operations set and reset when the PowerPC processor is + changed. + +==================== Branch work159, patch #2 ==================== + +Add power11 aux vector and tests. + +This patch adds the support for using __builtin_cpu_is ("power11"). + +This patch also adds support for the gcc driver program to detect when it is +running on a power11 system and transforming -mcpu=native into -mcpu=power11. + +This patch adds a few simple tests for power11 support, assuming the assembler +supports the -mpower11 option. + +2024-02-21 Michael Meissner + +gcc/ + + * config/rs6000/driver-rs6000.c (asm_names): Add power11 support. + * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Remove comment saying + this is not yet official. + (PPC_PLATFORM_POWER11): Add power11 support. + * config/rs6000/rs6000-builtin.cc (cpu_is_info): Likewise. + +gcc/testsuite/ + + * lib/target-support.exp (check_effective_target_power11_ok): Add + power11 support. + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + +==================== Branch work159, patch #1 ==================== + +Add -mcpu=power11 and -mcpu=future support. + +This patch adds support for -mcpu=power11 and -mtune=power11. At the current +time, no new instructions are implemented. The tuning for the power11 processor +is exactly the same as for power10. + +If -mcpu=power11 is used, the macro _ARCH_PWR11 will be defined. + +In order to use -mcpu=power11, you will need an assembler that supports the +-mpower11 option. + +In addition, this patch adds support for -mcpu=future and -mtune=future. This +is to allow for a way to experiment with future additions to the PowerPC +computers that may or may not become part of the official PowerPC processor line +up. At the current time, no new instructions are implemented. The tuning for +the future processor is exactly the same as for power10. + +If -mcpu=future is used, the macro _ARCH_PWR_FUTURE will be defined. + +In order to use -mcpu=future, you will need an assembler that supports the +-mfuture option. + +2024-02-21 Michael Meissner + +gcc/ + + * config.gcc (powerpc*-*-*, rs6000-*-*): Add support for power11 and + future processors. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR11 if -mcpu=power11 and _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): Add support + for -mcpu=power11. + (ISA_FUTURE_MASKS_SERVER): Add support for -mcpu=future. + (POWERPC_MASKS): Add support for -mcpu=power11 and -mcpu=future. + (power11 cpu): Add power11 cpu. + (future cpu): Add future cpu. + * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): New macro. + (PROCESSOR_FUTURE): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_machine_from_flags): If -mcpu=power11, + emit .machine power11. If -mcpu=future emit .machine future. + (rs6000_opt_masks): Add support for power11 and future ISA bits. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mfuture to the assembler + if -mcpu=future. Pass -mpower11 to the assembler if -mcpu=power11. + * config/rs6000/rs6000.opt (-mpower11): New internal ISA bit for + power11 cpu. + (-mfuture): New internal ISA bit for future cpu. + * doc/invoke.texi (PowerPC options): Document -mcpu=future and + -mcpu=power11. + ==================== Branch work159, baseline ==================== +Add ChangeLog.meissner and REVISION. + +2024-02-20 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + 2024-02-20 Michael Meissner Clone branch