From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1035) id BE7AF3858299; Fri, 23 Feb 2024 13:54:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BE7AF3858299 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1708696464; bh=quGpdxDvyhtdLdNbnwFlyxeA3VJsRZrCOqlwUEGbxYE=; h=From:To:Subject:Date:From; b=dC7ZtF4/KD0wajK77AvCmFPoqhSVyKUihFaO2sfhp9XNOwbCtOGRBjLyB2X5P5Rko gQcHPY0E/t3c7DPZwAAPnum157MPzlyGptCxYxf5TaoNTPgbx7tswet6puzWW4Jr38 fP+Sgaik3GG6afjSOtuzvUkD9/HCetLSkuIaJT68= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Earnshaw To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-11251] arm: fix ICE with vectorized reciprocal division [PR108120] X-Act-Checkin: gcc X-Git-Author: Richard Earnshaw X-Git-Refname: refs/heads/releases/gcc-11 X-Git-Oldrev: 3aec8d2bdc8cbb599ea820e4940619d0e7f69c90 X-Git-Newrev: 98032b3e320a5b63309d6a843f6e97fb0506953a Message-Id: <20240223135424.BE7AF3858299@sourceware.org> Date: Fri, 23 Feb 2024 13:54:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:98032b3e320a5b63309d6a843f6e97fb0506953a commit r11-11251-g98032b3e320a5b63309d6a843f6e97fb0506953a Author: Richard Earnshaw Date: Thu Feb 22 16:47:20 2024 +0000 arm: fix ICE with vectorized reciprocal division [PR108120] The expand pattern for reciprocal division was enabled for all math optimization modes, but the patterns it was generating were not enabled unless -funsafe-math-optimizations were enabled, this leads to an ICE when the pattern we generate cannot be recognized. Fixed by only enabling vector division when doing unsafe math. gcc: PR target/108120 * config/arm/neon.md (div3): Rename from div3. Gate with ARM_HAVE_NEON__ARITH. gcc/testsuite: PR target/108120 * gcc.target/arm/neon-recip-div-1.c: New file. (cherry picked from commit 016c4eed368b80a97101f6156ed99e4c5474fbb7) Diff: --- gcc/config/arm/neon.md | 4 ++-- gcc/testsuite/gcc.target/arm/neon-recip-div-1.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index c0dcec80bc6d..e0309e07aa62 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -513,11 +513,11 @@ Enabled with -funsafe-math-optimizations -freciprocal-math and disabled for -Os since it increases code size . */ -(define_expand "div3" +(define_expand "div3" [(set (match_operand:VCVTF 0 "s_register_operand") (div:VCVTF (match_operand:VCVTF 1 "s_register_operand") (match_operand:VCVTF 2 "s_register_operand")))] - "TARGET_NEON && !optimize_size + "ARM_HAVE_NEON__ARITH && !optimize_size && flag_reciprocal_math" { rtx rec = gen_reg_rtx (mode); diff --git a/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c b/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c new file mode 100644 index 000000000000..e15c3ca5fe9d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3 -freciprocal-math -fno-unsafe-math-optimizations -save-temps" } */ +/* { dg-add-options arm_neon } */ + +int *a; +int n; +void b() { + int c; + for (c = 0; c < 100000; c++) + a[c] = (float)c / n; +} +/* We should not ICE, or get a vectorized reciprocal instruction when unsafe + math optimizations are disabled. */ +/* { dg-final { scan-assembler-not "vrecpe\\.f32\\t\[qd\].*" } } */ +/* { dg-final { scan-assembler-not "vrecps\\.f32\\t\[qd\].*" } } */