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From: Andre Simoes Dias Vieira <avieira@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r14-9303] arm: Fix a wrong attribute use and remove unused unspecs and iterators
Date: Mon, 4 Mar 2024 18:16:53 +0000 (GMT) [thread overview]
Message-ID: <20240304181653.3F8963858C33@sourceware.org> (raw)
https://gcc.gnu.org/g:8e92b66fdba16faf0d5ace279f1c02cec6a5cc23
commit r14-9303-g8e92b66fdba16faf0d5ace279f1c02cec6a5cc23
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Wed Feb 14 17:01:11 2024 +0000
arm: Fix a wrong attribute use and remove unused unspecs and iterators
This patch fixes the erroneous use of a mode attribute without a mode iterator
in the pattern and removes unused unspecs and iterators.
gcc/ChangeLog:
* config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
VMLALDAVAXQ_U cases.
(VMLALDAVXQ): Remove iterator.
(VMLALDAVXQ_P): Likewise.
(VMLALDAVAXQ): Likewise.
* config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
mode iterator attribute with V4BI mode.
* config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
VMLALDAVAXQ_U): Remove unused unspecs.
Diff:
---
gcc/config/arm/iterators.md | 9 +++------
gcc/config/arm/mve.md | 2 +-
gcc/config/arm/unspecs.md | 3 ---
3 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index da49bd64f17..8d066fcf05d 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -2369,7 +2369,7 @@
(VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s")
(VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u")
(VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u")
- (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s")
+ (VMLALDAVQ_S "s") (VMLALDAVXQ_S "s")
(VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u")
(VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u")
(VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s")
@@ -2411,8 +2411,8 @@
(VREV16Q_M_S "s") (VREV16Q_M_U "u")
(VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u")
(VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u")
- (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u")
- (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u")
+ (VRSHRNBQ_N_U "u")
+ (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u")
(VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s")
(VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u")
(VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s")
@@ -2761,7 +2761,6 @@
(define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U])
(define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U])
(define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S])
-(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S])
(define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S])
(define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U])
(define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S])
@@ -2816,11 +2815,9 @@
(define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S])
(define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S])
(define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U])
-(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S])
(define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S])
(define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S])
(define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S])
-(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U])
(define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U])
(define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U])
(define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d7bdcd862f8..9fe51298cdc 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -4605,7 +4605,7 @@
[(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
(unspec:V4SI
[(match_operand:V4SF 1 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
+ (match_operand:V4BI 2 "vpr_register_operand" "Up")
(match_dup 0)]
VSTRWQ_F))]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index b9db306c067..46ac8b37157 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -717,7 +717,6 @@
VCVTBQ_F16_F32
VCVTTQ_F16_F32
VMLALDAVQ_U
- VMLALDAVXQ_U
VMLALDAVXQ_S
VMLALDAVQ_S
VMLSLDAVQ_S
@@ -934,7 +933,6 @@
VSHRNBQ_N_S
VRSHRNBQ_N_S
VRSHRNBQ_N_U
- VMLALDAVXQ_P_U
VMLALDAVXQ_P_S
VQMOVNTQ_M_U
VQMOVNTQ_M_S
@@ -943,7 +941,6 @@
VQSHRNTQ_N_U
VQSHRNTQ_N_S
VMLALDAVAXQ_S
- VMLALDAVAXQ_U
VSHRNTQ_N_S
VSHRNTQ_N_U
VCVTBQ_M_F16_F32
reply other threads:[~2024-03-04 18:16 UTC|newest]
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