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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work161-dmf)] Revert changes
Date: Tue, 5 Mar 2024 00:10:44 +0000 (GMT) [thread overview]
Message-ID: <20240305001044.7B89C3858C66@sourceware.org> (raw)
https://gcc.gnu.org/g:2d441d11bcaeaae42f04a6a59143c7ca8b143a64
commit 2d441d11bcaeaae42f04a6a59143c7ca8b143a64
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Mar 4 19:10:39 2024 -0500
Revert changes
Diff:
---
gcc/config/rs6000/mma.md | 159 ++++----------------------
gcc/config/rs6000/predicates.md | 21 +---
gcc/config/rs6000/rs6000-builtin.cc | 5 +-
gcc/config/rs6000/rs6000.cc | 221 +++++++-----------------------------
gcc/config/rs6000/rs6000.h | 43 +------
gcc/config/rs6000/rs6000.md | 12 +-
6 files changed, 71 insertions(+), 390 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 33c1baeda5e..49cf5f8fe43 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -91,8 +91,6 @@
UNSPEC_MMA_XVI8GER4SPP
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
- UNSPEC_MMA_DMSETDMRZ
- UNSPEC_DM_ASSEMBLE
])
(define_c_enum "unspecv"
@@ -316,9 +314,7 @@
(set_attr "length" "*,*,8")])
\f
-;; Vector quad support. Under the original MMA, XOmode can only live in VSX
-;; registers 0..31. With dense math, XOmode can live in either VSX registers
-;; (0..63) or DMR registers.
+;; Vector quad support. XOmode can only live in FPRs.
(define_expand "movxo"
[(set (match_operand:XO 0 "nonimmediate_operand")
(match_operand:XO 1 "input_operand"))]
@@ -343,10 +339,10 @@
gcc_assert (false);
})
-(define_insn_and_split "*movxo_nodm"
+(define_insn_and_split "*movxo"
[(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
(match_operand:XO 1 "input_operand" "ZwO,d,d"))]
- "TARGET_MMA_NO_DENSE_MATH
+ "TARGET_MMA
&& (gpc_reg_operand (operands[0], XOmode)
|| gpc_reg_operand (operands[1], XOmode))"
"@
@@ -363,31 +359,6 @@
(set_attr "length" "*,*,16")
(set_attr "max_prefixed_insns" "2,2,*")])
-(define_insn_and_split "*movxo_dm"
- [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,QwO,wa,wD,wD,wa")
- (match_operand:XO 1 "input_operand" "QwO,wa, wa,wa,wD,wD"))]
- "TARGET_MMA_DENSE_MATH
- && (gpc_reg_operand (operands[0], XOmode)
- || gpc_reg_operand (operands[1], XOmode))"
- "@
- #
- #
- #
- dmxxinstdmr512 %0,%1,%Y1,0
- dmmr %0,%1
- dmxxextfdmr512 %0,%Y0,%1,0"
- "&& reload_completed
- && !dmr_operand (operands[0], XOmode)
- && !dmr_operand (operands[1], XOmode)"
- [(const_int 0)]
-{
- rs6000_split_multireg_move (operands[0], operands[1]);
- DONE;
-}
- [(set_attr "type" "vecload,vecstore,veclogical,mma,mma,mma")
- (set_attr "length" "*,*,16,*,*,*")
- (set_attr "max_prefixed_insns" "2,2,*,*,*,*")])
-
(define_expand "vsx_assemble_pair"
[(match_operand:OO 0 "vsx_register_operand")
(match_operand:V16QI 1 "mma_assemble_input_operand")
@@ -455,47 +426,25 @@
})
(define_expand "mma_assemble_acc"
- [(match_operand:XO 0 "register_operand")
+ [(match_operand:XO 0 "fpr_reg_operand")
(match_operand:V16QI 1 "mma_assemble_input_operand")
(match_operand:V16QI 2 "mma_assemble_input_operand")
(match_operand:V16QI 3 "mma_assemble_input_operand")
(match_operand:V16QI 4 "mma_assemble_input_operand")]
"TARGET_MMA"
{
- rtx op0 = operands[0];
- rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op3 = operands[3];
- rtx op4 = operands[4];
-
- if (TARGET_DENSE_MATH)
- {
- rtx vpair1 = gen_reg_rtx (OOmode);
- rtx vpair2 = gen_reg_rtx (OOmode);
- if (WORDS_BIG_ENDIAN)
- {
- emit_insn (gen_vsx_assemble_pair (vpair1, op1, op2));
- emit_insn (gen_vsx_assemble_pair (vpair2, op3, op4));
- emit_insn (gen_mma_assemble_acc_dm (op0, vpair1, vpair2));
- }
- else
- {
- emit_insn (gen_vsx_assemble_pair (vpair1, op4, op3));
- emit_insn (gen_vsx_assemble_pair (vpair2, op2, op1));
- emit_insn (gen_mma_assemble_acc_dm (op0, vpair1, vpair2));
- }
- }
-
- else
- emit_insn (gen_mma_assemble_acc_nodm (op0, op1, op2, op3, op4));
-
+ rtx src = gen_rtx_UNSPEC_VOLATILE (XOmode,
+ gen_rtvec (4, operands[1], operands[2],
+ operands[3], operands[4]),
+ UNSPECV_MMA_ASSEMBLE);
+ emit_move_insn (operands[0], src);
DONE;
})
;; We cannot update the four output registers atomically, so mark the output
-;; as an early clobber so we don't accidentally clobber the input operands.
+;; as an early clobber so we don't accidentally clobber the input operands. */
-(define_insn_and_split "mma_assemble_acc_nodm"
+(define_insn_and_split "*mma_assemble_acc"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
(unspec_volatile:XO
[(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa")
@@ -503,7 +452,7 @@
(match_operand:V16QI 3 "mma_assemble_input_operand" "mwa")
(match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")]
UNSPECV_MMA_ASSEMBLE))]
- "TARGET_MMA_NO_DENSE_MATH"
+ "TARGET_MMA"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -516,31 +465,6 @@
DONE;
})
-;; On a system with dense math, we build the accumulators from two vector
-;; pairs.
-
-(define_insn_and_split "mma_assemble_acc_dm"
- [(set (match_operand:XO 0 "register_operand" "=wD,?wa")
- (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa,mwa")
- (match_operand:OO 2 "vsx_register_operand" "wa,mwa")]
- UNSPEC_DM_ASSEMBLE))]
- "TARGET_MMA_DENSE_MATH"
- "@
- dmxxinstdmr512 %0,%1,%2,0
- #"
- "&& reload_completed && vsx_register_operand (operands[0], XOmode)"
- [(set (match_dup 3) (match_dup 1))
- (set (match_dup 4) (match_dup 2))]
-{
- int r = reg_or_subregno (operands[0]);
- int hi = (!WORDS_BIG_ENDIAN);
- int lo = 1 - hi;
- operands[3] = gen_rtx_REG (OOmode, r + (hi * 2));
- operands[4] = gen_rtx_REG (OOmode, r + (lo * 2));
-}
- [(set_attr "type" "mma")
- (set_attr "length" "*,16")])
-
(define_expand "mma_disassemble_acc"
[(match_operand:V16QI 0 "mma_disassemble_output_operand")
(match_operand:XO 1 "fpr_reg_operand")
@@ -573,72 +497,29 @@
DONE;
})
-;; MMA instructions that do not use their accumulators as an input, still must
-;; not allow their vector operands to overlap the registers used by the
-;; accumulator. We enforce this by marking the output as early clobber. The
-;; prime and de-prime instructions are not needed on systems with dense math
-;; registers.
+;; MMA instructions that do not use their accumulators as an input, still
+;; must not allow their vector operands to overlap the registers used by
+;; the accumulator. We enforce this by marking the output as early clobber.
(define_insn "mma_<acc>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
- "TARGET_MMA_NO_DENSE_MATH"
+ "TARGET_MMA"
"<acc> %A0"
[(set_attr "type" "mma")])
;; We can't have integer constants in XOmode so we wrap this in an
-;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't need
-;; to disable optimization and we can do a normal UNSPEC.
+;; UNSPEC_VOLATILE.
-(define_expand "mma_xxsetaccz"
- [(set (match_operand:XO 0 "register_operand")
+(define_insn "mma_xxsetaccz"
+ [(set (match_operand:XO 0 "accumulator_operand" "=wD")
(unspec_volatile:XO [(const_int 0)]
UNSPECV_MMA_XXSETACCZ))]
"TARGET_MMA"
-{
- if (TARGET_DENSE_MATH)
- {
- emit_insn (gen_mma_dmsetaccz (operands[0]));
- DONE;
- }
-})
-
-(define_insn "*mma_xxsetaccz_nodm"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
- (unspec_volatile:XO [(const_int 0)]
- UNSPECV_MMA_XXSETACCZ))]
- "TARGET_MMA_NO_DENSE_MATH"
"xxsetaccz %A0"
[(set_attr "type" "mma")])
-
-;; If we have dense math registers, allow VSX registers as well as the
-;; accumulators. This means if we are setting things up by clearing an
-;; accumulator and then just storing it for later, we don't have to do a
-;; dmsetdmrz and a dmxxextfdmr512 just to store the accumulator.
-(define_insn_and_split "mma_dmsetaccz"
- [(set (match_operand:XO 0 "register_operand" "=wD,?wa")
- (unspec:XO [(const_int 0)]
- UNSPEC_MMA_DMSETDMRZ))]
- "TARGET_MMA_DENSE_MATH"
- "@
- dmsetdmrz %0
- #"
- "&& reload_completed && vsx_register_operand (operands[0], XOmode)"
- [(const_int 0)]
-{
- int r = reg_or_subregno (operands[0]);
- rtx zero = CONST0_RTX (V2DFmode);
- emit_move_insn (gen_rtx_REG (V2DFmode, r), zero);
- emit_move_insn (gen_rtx_REG (V2DFmode, r + 1), zero);
- emit_move_insn (gen_rtx_REG (V2DFmode, r + 2), zero);
- emit_move_insn (gen_rtx_REG (V2DFmode, r + 3), zero);
- DONE;
-}
- [(set_attr "type" "mma")
- (set_attr "length" "*,16")])
-
(define_insn "mma_<vv>"
[(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b325000690b..2ef4256c72b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -186,23 +186,8 @@
return VLOGICAL_REGNO_P (REGNO (op));
})
-;; Return 1 if op is a DMR register
-(define_predicate "dmr_operand"
- (match_operand 0 "register_operand")
-{
- if (!REG_P (op))
- return 0;
-
- if (!HARD_REGISTER_P (op))
- return 1;
-
- return DMR_REGNO_P (REGNO (op));
-})
-
;; Return 1 if op is an accumulator. On power10 systems, the accumulators
-;; overlap with the FPRs, while on systems with dense math, the accumulators
-;; are separate dense math registers and do not overlap with the FPR
-;; registers..
+;; overlap with the FPRs.
(define_predicate "accumulator_operand"
(match_operand 0 "register_operand")
{
@@ -213,9 +198,7 @@
return 1;
int r = REGNO (op);
- return (TARGET_MMA_DENSE_MATH
- ? DMR_REGNO_P (r)
- : FP_REGNO_P (r) && (r & 3) == 0);
+ return FP_REGNO_P (r) && (r & 3) == 0;
})
;; Return 1 if op is the carry register.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index cf96ec6a869..f3ba1eccdbd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -1122,9 +1122,8 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi,
}
/* If we're disassembling an accumulator into a different type, we need
- to emit a xxmfacc instruction now, since we cannot do it later. If we
- have dense math registers, we don't need to do this. */
- if (fncode == RS6000_BIF_DISASSEMBLE_ACC && !TARGET_DENSE_MATH)
+ to emit a xxmfacc instruction now, since we cannot do it later. */
+ if (fncode == RS6000_BIF_DISASSEMBLE_ACC)
{
new_decl = rs6000_builtin_decls[RS6000_BIF_XXMFACC_INTERNAL];
new_call = gimple_build_call (new_decl, 1, src);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e83c507a8d5..8baaacad0f2 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -292,8 +292,7 @@ enum rs6000_reg_type {
ALTIVEC_REG_TYPE,
FPR_REG_TYPE,
SPR_REG_TYPE,
- CR_REG_TYPE,
- DMR_REG_TYPE
+ CR_REG_TYPE
};
/* Map register class to register type. */
@@ -307,23 +306,22 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
/* Register classes we care about in secondary reload or go if legitimate
- address. We only need to worry about GPR, FPR, Altivec, and DMR registers
- here, along an ANY field that is the OR of the 4 register classes. */
+ address. We only need to worry about GPR, FPR, and Altivec registers here,
+ along an ANY field that is the OR of the 3 register classes. */
enum rs6000_reload_reg_type {
RELOAD_REG_GPR, /* General purpose registers. */
RELOAD_REG_FPR, /* Traditional floating point regs. */
RELOAD_REG_VMX, /* Altivec (VMX) registers. */
- RELOAD_REG_DMR, /* DMR registers. */
- RELOAD_REG_ANY, /* OR of GPR/FPR/VMX/DMR masks. */
+ RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
N_RELOAD_REG
};
-/* For setting up register classes, loop through the 4 register classes mapping
+/* For setting up register classes, loop through the 3 register classes mapping
into real registers, and skip the ANY class, which is just an OR of the
bits. */
#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
-#define LAST_RELOAD_REG_CLASS RELOAD_REG_DMR
+#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
/* Map reload register type to a register in the register class. */
struct reload_reg_map_type {
@@ -335,7 +333,6 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
{ "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
{ "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
{ "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
- { "DMR", FIRST_DMR_REGNO }, /* RELOAD_REG_DMR. */
{ "Any", -1 }, /* RELOAD_REG_ANY. */
};
@@ -1229,8 +1226,6 @@ char rs6000_reg_names[][8] =
"0", "1", "2", "3", "4", "5", "6", "7",
/* vrsave vscr sfp */
"vrsave", "vscr", "sfp",
- /* DMRs */
- "0", "1", "2", "3", "4", "5", "6", "7",
};
#ifdef TARGET_REGNAMES
@@ -1257,8 +1252,6 @@ static const char alt_reg_names[][8] =
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
/* vrsave vscr sfp */
"vrsave", "vscr", "sfp",
- /* DMRs */
- "%dmr0", "%dmr1", "%dmr2", "%dmr3", "%dmr4", "%dmr5", "%dmr6", "%dmr7",
};
#endif
@@ -1843,9 +1836,6 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
- else if (DMR_REGNO_P (regno))
- reg_size = UNITS_PER_DMR_WORD;
-
else
reg_size = UNITS_PER_WORD;
@@ -1867,36 +1857,9 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
if (mode == OOmode)
return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0);
- /* On ISA 3.1 (power10), MMA accumulator modes need FPR registers divisible
- by 4.
-
- If dense math is enabled, allow all VSX registers plus the DMR registers.
- We need to make sure we don't cross between the boundary of FPRs and
- traditional Altiviec registers. */
+ /* MMA accumulator modes need FPR registers divisible by 4. */
if (mode == XOmode)
- {
- if (TARGET_MMA)
- {
- if (FP_REGNO_P (regno) && (regno & 3) == 0)
- return 1;
-
- if (TARGET_DENSE_MATH)
- {
- if (DMR_REGNO_P (regno))
- return 1;
-
- if (ALTIVEC_REGNO_P (regno))
- return ((regno & 1) == 0 && regno <= LAST_ALTIVEC_REGNO - 3);
- }
- }
-
- else
- return 0;
- }
-
- /* No other types other than XOmode can go in DMRs. */
- if (DMR_REGNO_P (regno))
- return 0;
+ return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0);
/* PTImode can only go in GPRs. Quad word memory operations require even/odd
register combinations, and use PTImode where we need to deal with quad
@@ -2339,7 +2302,6 @@ rs6000_debug_reg_global (void)
rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
LAST_ALTIVEC_REGNO,
"vs");
- rs6000_debug_reg_print (FIRST_DMR_REGNO, LAST_DMR_REGNO, "dmr");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
@@ -2666,21 +2628,6 @@ rs6000_setup_reg_addr_masks (void)
addr_mask = 0;
reg = reload_reg_map[rc].reg;
- /* Special case DMR registers. */
- if (rc == RELOAD_REG_DMR)
- {
- if (TARGET_DENSE_MATH && m2 == XOmode)
- {
- addr_mask = RELOAD_REG_VALID;
- reg_addr[m].addr_mask[rc] = addr_mask;
- any_addr_mask |= addr_mask;
- }
- else
- reg_addr[m].addr_mask[rc] = 0;
-
- continue;
- }
-
/* Can mode values go in the GPR/FPR/Altivec registers? */
if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
{
@@ -2831,9 +2778,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
rs6000_regno_regclass[r] = CR_REGS;
- for (r = FIRST_DMR_REGNO; r <= LAST_DMR_REGNO; ++r)
- rs6000_regno_regclass[r] = DM_REGS;
-
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
@@ -2858,7 +2802,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
- reg_class_to_reg_type[(int)DM_REGS] = DMR_REG_TYPE;
if (TARGET_VSX)
{
@@ -3045,11 +2988,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
- /* Support for the accumulator registers, either FPR registers (aka original
- mma) or DMR registers (dense math). */
if (TARGET_MMA)
- rs6000_constraints[RS6000_CONSTRAINT_wD]
- = TARGET_DENSE_MATH ? DM_REGS : FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
@@ -12376,11 +12316,6 @@ rs6000_secondary_reload_memory (rtx addr,
addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
& ~RELOAD_REG_AND_M16);
- /* DMR registers use VSX registers for memory operations, and need to
- generate some extra instructions. */
- else if (rclass == DM_REGS)
- return 2;
-
/* If the register allocator hasn't made up its mind yet on the register
class to use, settle on defaults to use. */
else if (rclass == NO_REGS)
@@ -12709,13 +12644,6 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
|| (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
return true;
- /* We can transfer between VSX registers and DMR registers without needing
- extra registers. */
- if (TARGET_DENSE_MATH && mode == XOmode
- && ((to_type == DMR_REG_TYPE && from_type == VSX_REG_TYPE)
- || (to_type == VSX_REG_TYPE && from_type == DMR_REG_TYPE)))
- return true;
-
return false;
}
@@ -13410,10 +13338,6 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
machine_mode mode = GET_MODE (x);
bool is_constant = CONSTANT_P (x);
- /* DMR registers can't be loaded or stored. */
- if (rclass == DM_REGS)
- return NO_REGS;
-
/* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
reload class for it. */
if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
@@ -13510,7 +13434,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
return VSX_REGS;
if (mode == XOmode)
- return TARGET_MMA_DENSE_MATH ? VSX_REGS : FLOAT_REGS;
+ return FLOAT_REGS;
if (GET_MODE_CLASS (mode) == MODE_INT)
return GENERAL_REGS;
@@ -13635,11 +13559,6 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
else
regno = -1;
- /* DMR registers don't have loads or stores. We have to go through the VSX
- registers to load XOmode (vector quad). */
- if (TARGET_MMA_DENSE_MATH && rclass == DM_REGS)
- return VSX_REGS;
-
/* If we have VSX register moves, prefer moving scalar values between
Altivec registers and GPR by going via an FPR (and then via memory)
instead of reloading the secondary memory address for Altivec moves. */
@@ -14153,19 +14072,8 @@ print_operand (FILE *file, rtx x, int code)
output_operand. */
case 'A':
- /* Write the MMA accumulator number associated with VSX register X. On
- dense math systems, only allow DMR accumulators, not accumulators
- overlapping with the FPR registers. */
- if (!REG_P (x))
- output_operand_lossage ("invalid %%A value");
- else if (TARGET_MMA_DENSE_MATH)
- {
- if (DMR_REGNO_P (REGNO (x)))
- fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
- else
- output_operand_lossage ("%%A operand is not a DMR");
- }
- else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
+ /* Write the MMA accumulator number associated with VSX register X. */
+ if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
output_operand_lossage ("invalid %%A value");
else
fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
@@ -22835,31 +22743,6 @@ rs6000_debug_address_cost (rtx x, machine_mode mode,
}
-/* Subroutine to determine the move cost of dense math registers. If we are
- moving to/from VSX_REGISTER registers, the cost is either 1 move (for
- 512-bit accumulators) or 2 moves (for 1,024 dmr registers). If we are
- moving to anything else like GPR registers, make the cost very high. */
-
-static int
-rs6000_dmr_register_move_cost (machine_mode mode, reg_class_t rclass)
-{
- const int reg_move_base = 2;
- HARD_REG_SET vsx_set = (reg_class_contents[rclass]
- & reg_class_contents[VSX_REGS]);
-
- if (TARGET_MMA_DENSE_MATH && !hard_reg_set_empty_p (vsx_set))
- {
- /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */
- if (mode == XOmode)
- return reg_move_base;
-
- else
- return reg_move_base * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
- }
-
- return 1000 * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
-}
-
/* A C expression returning the cost of moving data from a register of class
CLASS1 to one of CLASS2. */
@@ -22873,28 +22756,17 @@ rs6000_register_move_cost (machine_mode mode,
if (TARGET_DEBUG_COST)
dbg_cost_ctrl++;
- HARD_REG_SET to_vsx, from_vsx;
- to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
- from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
-
- /* Special case DMR registers, that can only move to/from VSX registers. */
- if (from == DM_REGS && to == DM_REGS)
- ret = 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
-
- else if (from == DM_REGS)
- ret = rs6000_dmr_register_move_cost (mode, to);
-
- else if (to == DM_REGS)
- ret = rs6000_dmr_register_move_cost (mode, from);
-
/* If we have VSX, we can easily move between FPR or Altivec registers,
otherwise we can only easily move within classes.
Do this first so we give best-case answers for union classes
containing both gprs and vsx regs. */
- else if (!hard_reg_set_empty_p (to_vsx)
- && !hard_reg_set_empty_p (from_vsx)
- && (TARGET_VSX
- || hard_reg_set_intersect_p (to_vsx, from_vsx)))
+ HARD_REG_SET to_vsx, from_vsx;
+ to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
+ from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
+ if (!hard_reg_set_empty_p (to_vsx)
+ && !hard_reg_set_empty_p (from_vsx)
+ && (TARGET_VSX
+ || hard_reg_set_intersect_p (to_vsx, from_vsx)))
{
int reg = FIRST_FPR_REGNO;
if (TARGET_VSX
@@ -22989,9 +22861,6 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
ret = 4 * hard_regno_nregs (32, mode);
else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
- else if (reg_classes_intersect_p (rclass, DM_REGS))
- ret = (rs6000_dmr_register_move_cost (mode, VSX_REGS)
- + rs6000_memory_move_cost (mode, VSX_REGS, false));
else
ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
@@ -24200,8 +24069,6 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
if (TARGET_HARD_FLOAT)
pressure_classes[n++] = FLOAT_REGS;
}
- if (TARGET_MMA_DENSE_MATH)
- pressure_classes[n++] = DM_REGS;
pressure_classes[n++] = CR_REGS;
pressure_classes[n++] = SPECIAL_REGS;
@@ -24366,10 +24233,6 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format)
return 67;
if (regno == 64)
return 64;
- /* XXX: This is a guess. The GCC register number for FIRST_DMR_REGNO is 111,
- but the frame pointer regnum uses that. */
- if (DMR_REGNO_P (regno))
- return regno - FIRST_DMR_REGNO + 112;
gcc_unreachable ();
}
@@ -27611,9 +27474,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
unsigned offset = 0;
unsigned size = GET_MODE_SIZE (reg_mode);
- /* If we are reading an accumulator register, we have to deprime it
- before we can access it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ /* If we are reading an accumulator register, we have to
+ deprime it before we can access it. */
+ if (TARGET_MMA
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27645,9 +27508,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_rtx_SET (dst2, src2));
}
- /* If we are writing an accumulator register, we have to prime it
- after we've written it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ /* If we are writing an accumulator register, we have to
+ prime it after we've written it. */
+ if (TARGET_MMA
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
@@ -27661,9 +27524,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
|| XINT (src, 1) == UNSPECV_MMA_ASSEMBLE);
gcc_assert (REG_P (dst));
if (GET_MODE (src) == XOmode)
- gcc_assert ((TARGET_MMA_DENSE_MATH
- ? VSX_REGNO_P (REGNO (dst))
- : FP_REGNO_P (REGNO (dst))));
+ gcc_assert (FP_REGNO_P (REGNO (dst)));
if (GET_MODE (src) == OOmode)
gcc_assert (VSX_REGNO_P (REGNO (dst)));
@@ -27716,9 +27577,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
emit_insn (gen_rtx_SET (dst_i, op));
}
- /* We are writing an accumulator register, so we have to prime it
- after we've written it unless we have dense math registers. */
- if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH)
+ /* We are writing an accumulator register, so we have to
+ prime it after we've written it. */
+ if (GET_MODE (src) == XOmode)
emit_insn (gen_mma_xxmtacc (dst, dst));
return;
@@ -27729,9 +27590,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
{
- /* If we are reading an accumulator register, we have to deprime it
- before we can access it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ /* If we are reading an accumulator register, we have to
+ deprime it before we can access it. */
+ if (TARGET_MMA
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27757,9 +27618,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
i * reg_mode_size)));
}
- /* If we are writing an accumulator register, we have to prime it after
- we've written it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH
+ /* If we are writing an accumulator register, we have to
+ prime it after we've written it. */
+ if (TARGET_MMA
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
}
@@ -27894,9 +27755,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
}
- /* If we are reading an accumulator register, we have to deprime it
- before we can access it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH && REG_P (src)
+ /* If we are reading an accumulator register, we have to
+ deprime it before we can access it. */
+ if (TARGET_MMA && REG_P (src)
&& GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
emit_insn (gen_mma_xxmfacc (src, src));
@@ -27926,9 +27787,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
j * reg_mode_size)));
}
- /* If we are writing an accumulator register, we have to prime it after
- we've written it unless we have dense math registers. */
- if (TARGET_MMA_NO_DENSE_MATH && REG_P (dst)
+ /* If we are writing an accumulator register, we have to
+ prime it after we've written it. */
+ if (TARGET_MMA && REG_P (dst)
&& GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
emit_insn (gen_mma_xxmtacc (dst, dst));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f5d144cbb12..fc3bd006c47 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -562,12 +562,6 @@ extern int rs6000_vector_align[];
&& TARGET_P8_VECTOR \
&& TARGET_POWERPC64)
-/* Whether we have dense math support. At present, we don't have a dense math
- ISA bit, just use the future bit set by -mcpu=future. */
-#define TARGET_DENSE_MATH TARGET_FUTURE
-#define TARGET_MMA_DENSE_MATH (TARGET_MMA && TARGET_DENSE_MATH)
-#define TARGET_MMA_NO_DENSE_MATH (TARGET_MMA && !TARGET_DENSE_MATH)
-
/* Inlining allows targets to define the meanings of bits in target_info
field of ipa_fn_summary by itself, the used bits for rs6000 are listed
below. */
@@ -665,7 +659,6 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16
-#define UNITS_PER_DMR_WORD 128
/* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int"
@@ -793,7 +786,7 @@ enum data_align { align_abi, align_opt, align_both };
Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
pointer, which is eventually eliminated in favor of SP or FP. */
-#define FIRST_PSEUDO_REGISTER 119
+#define FIRST_PSEUDO_REGISTER 111
/* Use standard DWARF numbering for DWARF debugging information. */
#define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
@@ -830,9 +823,7 @@ enum data_align { align_abi, align_opt, align_both };
/* cr0..cr7 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* vrsave vscr sfp */ \
- 1, 1, 1, \
- /* DMR registers. */ \
- 0, 0, 0, 0, 0, 0, 0, 0 \
+ 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -856,9 +847,7 @@ enum data_align { align_abi, align_opt, align_both };
/* cr0..cr7 */ \
1, 1, 0, 0, 0, 1, 1, 1, \
/* vrsave vscr sfp */ \
- 0, 0, 0, \
- /* DMR registers. */ \
- 0, 0, 0, 0, 0, 0, 0, 0 \
+ 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -895,7 +884,6 @@ enum data_align { align_abi, align_opt, align_both };
v2 (not saved; incoming vector arg reg; return value)
v19 - v14 (not saved or used for anything)
v31 - v20 (saved; order given to save least number)
- dmr0 - dmr7 (not saved)
vrsave, vscr (fixed)
sfp (fixed)
*/
@@ -938,9 +926,6 @@ enum data_align { align_abi, align_opt, align_both };
66, \
83, 82, 81, 80, 79, 78, \
95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
- /* DMR registers. */ \
- 111, 112, 113, 114, 115, 116, 117, 118, \
- /* Vrsave, vscr, sfp. */ \
108, 109, \
110 \
}
@@ -967,9 +952,6 @@ enum data_align { align_abi, align_opt, align_both };
/* True if register is a VSX register. */
#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
-/* True if register is a DMR register. */
-#define DMR_REGNO_P(N) ((N) >= FIRST_DMR_REGNO && (N) <= LAST_DMR_REGNO)
-
/* Alternate name for any vector register supporting floating point, no matter
which instruction set(s) are available. */
#define VFLOAT_REGNO_P(N) \
@@ -1105,7 +1087,6 @@ enum reg_class
FLOAT_REGS,
ALTIVEC_REGS,
VSX_REGS,
- DM_REGS,
VRSAVE_REGS,
VSCR_REGS,
GEN_OR_FLOAT_REGS,
@@ -1135,7 +1116,6 @@ enum reg_class
"FLOAT_REGS", \
"ALTIVEC_REGS", \
"VSX_REGS", \
- "DM_REGS", \
"VRSAVE_REGS", \
"VSCR_REGS", \
"GEN_OR_FLOAT_REGS", \
@@ -1170,8 +1150,6 @@ enum reg_class
{ 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
/* VSX_REGS. */ \
{ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
- /* DM_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 }, \
/* VRSAVE_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
/* VSCR_REGS. */ \
@@ -1199,7 +1177,7 @@ enum reg_class
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff } \
+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
}
/* The same information, inverted:
@@ -2100,16 +2078,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[108][0], /* vrsave */ \
&rs6000_reg_names[109][0], /* vscr */ \
\
- &rs6000_reg_names[110][0], /* sfp */ \
- \
- &rs6000_reg_names[111][0], /* dmr0 */ \
- &rs6000_reg_names[112][0], /* dmr1 */ \
- &rs6000_reg_names[113][0], /* dmr2 */ \
- &rs6000_reg_names[114][0], /* dmr3 */ \
- &rs6000_reg_names[115][0], /* dmr4 */ \
- &rs6000_reg_names[116][0], /* dmr5 */ \
- &rs6000_reg_names[117][0], /* dmr6 */ \
- &rs6000_reg_names[118][0], /* dmr7 */ \
+ &rs6000_reg_names[110][0] /* sfp */ \
}
/* Table of additional register names to use in user input. */
@@ -2163,8 +2132,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \
{"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \
{"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \
- {"dmr0", 111}, {"dmr1", 112}, {"dmr2", 113}, {"dmr3", 114}, \
- {"dmr4", 115}, {"dmr5", 116}, {"dmr6", 117}, {"dmr7", 118}, \
}
/* This is how to output an element of a case-vector that is relative. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 99e6515ba1d..bc8bc6ab060 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -51,8 +51,6 @@
(VRSAVE_REGNO 108)
(VSCR_REGNO 109)
(FRAME_POINTER_REGNUM 110)
- (FIRST_DMR_REGNO 111)
- (LAST_DMR_REGNO 118)
])
;;
@@ -357,7 +355,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dm,not_dm"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -405,14 +403,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "dm")
- (match_test "TARGET_DENSE_MATH"))
- (const_int 1)
-
- (and (eq_attr "isa" "not_dm")
- (match_test "!TARGET_DENSE_MATH"))
- (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
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