[gcc r14-9322] arm: check for low register before applying peephole [PR113510]

[gcc r14-9322] arm: check for low register before applying peephole [PR113510]

[Richard Earnshaw]

https://gcc.gnu.org/g:067a012bde15bfb62d9af309d9d524ebfe91b705

commit r14-9322-g067a012bde15bfb62d9af309d9d524ebfe91b705
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Tue Mar 5 17:21:43 2024 +0000

    arm: check for low register before applying peephole [PR113510]
    
    For thumb1, when using a peephole to fuse
    
            mov reg, #const
            add reg, reg, SP
    
    into
    
            add reg, SP, #const
    
    we must first check that reg is a low register, otherwise we will ICE
    when trying to recognize the resulting insn.
    
    gcc/ChangeLog:
    
            PR target/113510
            * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
            low_register_operand.

Diff:
---
 gcc/config/arm/thumb1.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 14d6df580af..d7074b43f60 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -113,7 +113,7 @@
 ;; Reloading and elimination of the frame pointer can
 ;; sometimes cause this optimization to be missed.
 (define_peephole2
-  [(set (match_operand:SI 0 "arm_general_register_operand" "")
+  [(set (match_operand:SI 0 "low_register_operand" "")
 	(match_operand:SI 1 "const_int_operand" ""))
    (set (match_dup 0)
 	(plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]