[gcc r14-9343] ARM: Fix conditional execution [PR113915]

[gcc r14-9343] ARM: Fix conditional execution [PR113915]

[Wilco Dijkstra]

https://gcc.gnu.org/g:b575f37a342cebb954aa85fa45df0604bfa1ada9

commit r14-9343-gb575f37a342cebb954aa85fa45df0604bfa1ada9
Author: Wilco Dijkstra <wilco.dijkstra@arm.com>
Date:   Wed Mar 6 17:35:16 2024 +0000

    ARM: Fix conditional execution [PR113915]
    
    By default most patterns can be conditionalized on Arm targets.  However
    Thumb-2 predication requires the "predicable" attribute be explicitly
    set to "yes".  Most patterns are shared between Arm and Thumb(-2) and are
    marked with "predicable".  Given this sharing, it does not make sense to
    use a different default for Arm.  So only consider conditional execution
    of instructions that have the predicable attribute set to yes.  This ensures
    that patterns not explicitly marked as such are never conditionally executed.
    
    gcc/ChangeLog:
            PR target/113915
            * config/arm/arm.md (NOCOND): Improve comment.
            (arm_rev*) Add predicable.
            * config/arm/arm.cc (arm_final_prescan_insn): Add check for
            PREDICABLE_YES.
    
    gcc/testsuite/ChangeLog:
            PR target/113915
            * gcc.target/arm/builtin-bswap-1.c: Fix test to allow conditional
            execution both for Arm and Thumb-2.

Diff:
---
 gcc/config/arm/arm.cc                          |  5 +++--
 gcc/config/arm/arm.md                          |  6 ++++++
 gcc/testsuite/gcc.target/arm/builtin-bswap-1.c | 15 ++++++---------
 3 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 1cd69268ee9..6a35fe44138 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -25613,11 +25613,12 @@ arm_final_prescan_insn (rtx_insn *insn)
 	      break;
 
 	    case INSN:
-	      /* Instructions using or affecting the condition codes make it
-		 fail.  */
+	      /* Check the instruction is explicitly marked as predicable.
+		 Instructions using or affecting the condition codes are not.  */
 	      scanbody = PATTERN (this_insn);
 	      if (!(GET_CODE (scanbody) == SET
 		    || GET_CODE (scanbody) == PARALLEL)
+		  || get_attr_predicable (this_insn) != PREDICABLE_YES
 		  || get_attr_conds (this_insn) != CONDS_NOCOND)
 		fail = TRUE;
 	      break;
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 814e871acea..1fd00146ca9 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -319,6 +319,8 @@
 ;
 ; NOCOND means that the instruction does not use or alter the condition
 ;   codes but can be converted into a conditionally exectuted instruction.
+;   Given that NOCOND is the default for most instructions if omitted,
+;   the attribute predicable must be set to yes as well.
 
 (define_attr "conds" "use,set,clob,unconditional,nocond"
 	(if_then_else
@@ -12559,6 +12561,7 @@
   revsh%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
    (set_attr "length" "2,2,4")
+   (set_attr "predicable" "no,yes,yes")
    (set_attr "type" "rev")]
 )
 
@@ -12572,6 +12575,7 @@
    rev16%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
    (set_attr "length" "2,2,4")
+   (set_attr "predicable" "no,yes,yes")
    (set_attr "type" "rev")]
 )
 
@@ -12596,6 +12600,7 @@
    rev16%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
    (set_attr "length" "2,2,4")
+   (set_attr "predicable" "no,yes,yes")
    (set_attr "type" "rev")]
 )
 
@@ -12616,6 +12621,7 @@
    rev16%?\t%0, %1"
   [(set_attr "arch" "t1,t2,32")
    (set_attr "length" "2,2,4")
+   (set_attr "predicable" "no,yes,yes")
    (set_attr "type" "rev")]
 )
 
diff --git a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c
index c1e7740d14d..1a311a6a5af 100644
--- a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c
+++ b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c
@@ -5,14 +5,11 @@
    of the instructions.  Add an -mtune option known to facilitate that.  */
 /* { dg-additional-options "-O2 -mtune=cortex-a53" } */
 /* { dg-final { scan-assembler-not "orr\[ \t\]" } } */
-/* { dg-final { scan-assembler-times "revsh\\t" 1 { target { arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "revshne\\t" 1 { target { arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "revsh\\t" 2 { target { ! arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "rev16\\t" 1 { target { arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "rev16ne\\t" 1 { target { arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "rev16\\t" 2 { target { ! arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "rev\\t" 2 { target { arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "revne\\t" 2 { target { arm_nothumb } } } }  */
-/* { dg-final { scan-assembler-times "rev\\t" 4 { target { ! arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "revsh\\t" 1 } }  */
+/* { dg-final { scan-assembler-times "revshne\\t" 1 } }  */
+/* { dg-final { scan-assembler-times "rev16\\t" 1 } }  */
+/* { dg-final { scan-assembler-times "rev16ne\\t" 1 } }  */
+/* { dg-final { scan-assembler-times "rev\\t" 2 } }  */
+/* { dg-final { scan-assembler-times "revne\\t" 2 } }  */
 
 #include "builtin-bswap.x"