[gcc r13-8450] aarch64: Fix TImode __sync_*_compare_and_exchange expansion with LSE [PR114310]

[gcc r13-8450] aarch64: Fix TImode __sync_*_compare_and_exchange expansion with LSE [PR114310]

[Jakub Jelinek]

https://gcc.gnu.org/g:1c907cee6163a3ec2c0edaebeace73e2d32835ee

commit r13-8450-g1c907cee6163a3ec2c0edaebeace73e2d32835ee
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Mar 14 14:09:20 2024 +0100

    aarch64: Fix TImode __sync_*_compare_and_exchange expansion with LSE [PR114310]
    
    The following testcase ICEs with LSE atomics.
    The problem is that the @atomic_compare_and_swap<mode> expander uses
    aarch64_reg_or_zero predicate for the desired operand, which is fine,
    given that for most of the modes and even for TImode in some cases
    it can handle zero immediate just fine, but the TImode
    @aarch64_compare_and_swap<mode>_lse just uses register_operand for
    that operand instead, again intentionally so, because the casp,
    caspa, caspl and caspal instructions need to use a pair of consecutive
    registers for the operand and xzr is just one register and we can't
    just store zero into the link register to emulate pair of zeros.
    
    So, the following patch fixes that by forcing the newval operand into
    a register for the TImode LSE case.
    
    2024-03-14  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/114310
            * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
            TImode force newval into a register.
    
            * gcc.dg/pr114310.c: New test.
    
    (cherry picked from commit 9349aefa1df7ae36714b7b9f426ad46e314892d1)

Diff:
---
 gcc/config/aarch64/aarch64.cc   |  2 ++
 gcc/testsuite/gcc.dg/pr114310.c | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index f546c48ae2d..f6d14cd791a 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -23081,6 +23081,8 @@ aarch64_expand_compare_and_swap (rtx operands[])
         rval = copy_to_mode_reg (r_mode, oldval);
       else
 	emit_move_insn (rval, gen_lowpart (r_mode, oldval));
+      if (mode == TImode)
+	newval = force_reg (mode, newval);
 
       emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem,
 						   newval, mod_s));
diff --git a/gcc/testsuite/gcc.dg/pr114310.c b/gcc/testsuite/gcc.dg/pr114310.c
new file mode 100644
index 00000000000..55edd800e42
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr114310.c
@@ -0,0 +1,20 @@
+/* PR target/114310 */
+/* { dg-do run { target int128 } } */
+
+volatile __attribute__((aligned (sizeof (__int128_t)))) __int128_t v = 10;
+
+int
+main ()
+{
+#if __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+  if (__sync_val_compare_and_swap (&v, (__int128_t) 10, (__int128_t) 0) != 10)
+    __builtin_abort ();
+  if (__sync_val_compare_and_swap (&v, (__int128_t) 10, (__int128_t) 15) != 0)
+    __builtin_abort ();
+  if (__sync_val_compare_and_swap (&v, (__int128_t) 0, (__int128_t) 42) != 0)
+    __builtin_abort ();
+  if (__sync_val_compare_and_swap (&v, (__int128_t) 31, (__int128_t) 35) != 42)
+    __builtin_abort ();
+#endif
+  return 0;
+}