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* [gcc(refs/users/meissner/heads/work163)] Revert all changes
@ 2024-03-19 21:28 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2024-03-19 21:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:acd5a60cccacc1b769f3afa835546368761cf431
commit acd5a60cccacc1b769f3afa835546368761cf431
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 19 17:28:40 2024 -0400
Revert all changes
Diff:
---
gcc/config.gcc | 4 +-
gcc/config/rs6000/aix71.h | 1 -
gcc/config/rs6000/aix72.h | 1 -
gcc/config/rs6000/aix73.h | 1 -
gcc/config/rs6000/driver-rs6000.cc | 2 -
gcc/config/rs6000/power10.md | 145 ++++++++++++++++++------------------
gcc/config/rs6000/rs6000-c.cc | 2 -
gcc/config/rs6000/rs6000-cpus.def | 5 --
gcc/config/rs6000/rs6000-opts.h | 3 +-
gcc/config/rs6000/rs6000-string.cc | 1 -
gcc/config/rs6000/rs6000-tables.opt | 3 -
gcc/config/rs6000/rs6000.cc | 30 ++------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 3 -
gcc/doc/invoke.texi | 2 +-
16 files changed, 85 insertions(+), 121 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6f31c789102..f8036b6476e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5568,7 +5568,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x | future \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 570ddcc451d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index 242ca94bd06..fe59f8319b4 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 2bd6b4bb3c4..1318b0b3662 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do { \
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc
index 07852fa50cf..f4900724b98 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,7 +441,6 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
- { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -471,7 +470,6 @@ static const struct asm_name asm_names[] = {
#else
{ "cell", "-mcell" },
- { "future", "-mfuture },
{ "power3", "-mppc64" },
{ "power4", "-mpower4" },
{ "power5", "-mpower5" },
diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md
index 1ec1bef0726..90312643858 100644
--- a/gcc/config/rs6000/power10.md
+++ b/gcc/config/rs6000/power10.md
@@ -1,5 +1,4 @@
-;; Scheduling description for the IBM POWER10 and POWER11 processors as well as
-;; potential future processors.
+;; Scheduling description for the IBM POWER10 and POWER11 processors.
;; Copyright (C) 2020-2024 Free Software Foundation, Inc.
;;
;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
@@ -98,12 +97,12 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-fused-load" 4
(and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-prefixed-load" 4
@@ -111,13 +110,13 @@
(eq_attr "update" "no")
(eq_attr "size" "!128")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-load-update" 4
(and (eq_attr "type" "load")
(eq_attr "update" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-fpload-double" 4
@@ -125,7 +124,7 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
(define_insn_reservation "power10-prefixed-fpload-double" 4
@@ -133,14 +132,14 @@
(eq_attr "update" "no")
(eq_attr "size" "64")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-fpload-update-double" 4
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "64")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
; SFmode loads are cracked and have additional 3 cycles over DFmode
@@ -149,27 +148,27 @@
(and (eq_attr "type" "fpload")
(eq_attr "update" "no")
(eq_attr "size" "32")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10")
(define_insn_reservation "power10-fpload-update-single" 7
(and (eq_attr "type" "fpload")
(eq_attr "update" "yes")
(eq_attr "size" "32")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-vecload" 4
(and (eq_attr "type" "vecload")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
; lxvp
(define_insn_reservation "power10-vecload-pair" 4
(and (eq_attr "type" "vecload")
(eq_attr "size" "256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
; Store Unit
@@ -179,12 +178,12 @@
(eq_attr "prefixed" "no")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
(define_insn_reservation "power10-fused-store" 0
(and (eq_attr "type" "fused_store_store")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
(define_insn_reservation "power10-prefixed-store" 0
@@ -192,52 +191,52 @@
(eq_attr "prefixed" "yes")
(eq_attr "size" "!128")
(eq_attr "size" "!256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
; Update forms have 2 cycle latency for updated addr reg
(define_insn_reservation "power10-store-update" 2
(and (eq_attr "type" "store,fpstore")
(eq_attr "update" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
; stxvp
(define_insn_reservation "power10-vecstore-pair" 0
(and (eq_attr "type" "vecstore")
(eq_attr "size" "256")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,stu0_power10+stu1_power10")
(define_insn_reservation "power10-larx" 4
(and (eq_attr "type" "load_l")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,LU_power10")
; All load quad forms
(define_insn_reservation "power10-lq" 4
(and (eq_attr "type" "load,load_l")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,LU_power10+SXU_power10")
(define_insn_reservation "power10-stcx" 0
(and (eq_attr "type" "store_c")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
; All store quad forms
(define_insn_reservation "power10-stq" 0
(and (eq_attr "type" "store,store_c")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,stu0_power10+stu1_power10")
(define_insn_reservation "power10-sync" 1
(and (eq_attr "type" "sync,isync")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
@@ -249,7 +248,7 @@
(define_insn_reservation "power10-alu" 2
(and (eq_attr "type" "add,exts,integer,logical,isel")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 4 cycle CR latency
(define_bypass 4 "power10-alu"
@@ -257,28 +256,28 @@
(define_insn_reservation "power10-fused_alu" 2
(and (eq_attr "type" "fused_arith_logical,fused_cmp_isel,fused_carry")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; paddi
(define_insn_reservation "power10-paddi" 2
(and (eq_attr "type" "add")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; Rotate/shift (non-record form)
(define_insn_reservation "power10-rot" 2
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; Record form rotate/shift
(define_insn_reservation "power10-rot-compare" 3
(and (eq_attr "type" "insert,shift")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 5 cycle CR latency
(define_bypass 5 "power10-rot-compare"
@@ -286,7 +285,7 @@
(define_insn_reservation "power10-alu2" 3
(and (eq_attr "type" "cntlz,popcnt,trap")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 5 cycle CR latency
(define_bypass 5 "power10-alu2"
@@ -294,24 +293,24 @@
(define_insn_reservation "power10-cmp" 2
(and (eq_attr "type" "cmp")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; Treat 'two' and 'three' types as 2 or 3 way cracked
(define_insn_reservation "power10-two" 4
(and (eq_attr "type" "two")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-three" 6
(and (eq_attr "type" "three")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_all_power10,EXU_power10")
(define_insn_reservation "power10-mul" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; 4 cycle MUL->MUL latency
(define_bypass 4 "power10-mul"
@@ -320,7 +319,7 @@
(define_insn_reservation "power10-mul-compare" 5
(and (eq_attr "type" "mul")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; 4 cycle MUL->MUL latency
(define_bypass 4 "power10-mul-compare"
@@ -332,13 +331,13 @@
(define_insn_reservation "power10-div" 12
(and (eq_attr "type" "div")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-div-compare" 12
(and (eq_attr "type" "div")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; 14 cycle CR latency
(define_bypass 14 "power10-div-compare"
@@ -346,34 +345,34 @@
(define_insn_reservation "power10-crlogical" 2
(and (eq_attr "type" "cr_logical")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfcrf" 2
(and (eq_attr "type" "mfcrf")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfcr" 3
(and (eq_attr "type" "mfcr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; Should differentiate between 1 cr field and > 1 since target of > 1 cr
; is cracked
(define_insn_reservation "power10-mtcr" 3
(and (eq_attr "type" "mtcr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mtjmpr" 3
(and (eq_attr "type" "mtjmpr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfjmpr" 2
(and (eq_attr "type" "mfjmpr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -381,126 +380,126 @@
(define_insn_reservation "power10-fpsimple" 3
(and (eq_attr "type" "fpsimple")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fp" 5
(and (eq_attr "type" "fp,dmul")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fpcompare" 3
(and (eq_attr "type" "fpcompare")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-sdiv" 22
(and (eq_attr "type" "sdiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-ddiv" 27
(and (eq_attr "type" "ddiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-sqrt" 26
(and (eq_attr "type" "ssqrt")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-dsqrt" 36
(and (eq_attr "type" "dsqrt")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vec-2cyc" 2
(and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-fused-vec" 2
(and (eq_attr "type" "fused_vector")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-veccmp" 3
(and (eq_attr "type" "veccmp")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecsimple" 2
(and (eq_attr "type" "vecsimple")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecnormal" 5
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qp" 12
(and (eq_attr "type" "vecfloat,vecdouble")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "prefixed" "no")
(eq_attr "dot" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecperm-compare" 3
(and (eq_attr "type" "vecperm")
(eq_attr "dot" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-prefixed-vecperm" 3
(and (eq_attr "type" "vecperm")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
(define_insn_reservation "power10-veccomplex" 6
(and (eq_attr "type" "veccomplex")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecfdiv" 24
(and (eq_attr "type" "vecfdiv")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-vecdiv" 27
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qpdiv" 56
(and (eq_attr "type" "vecdiv")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-qpmul" 24
(and (eq_attr "type" "qmul")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mtvsr" 2
(and (eq_attr "type" "mtvsr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-mfvsr" 2
(and (eq_attr "type" "mfvsr")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -508,26 +507,26 @@
; Branch is 2 cycles, grouped with STU for issue
(define_insn_reservation "power10-branch" 2
(and (eq_attr "type" "jmpreg,branch")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,STU_power10")
(define_insn_reservation "power10-fused-branch" 3
(and (eq_attr "type" "fused_mtbc")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,STU_power10")
; Crypto
(define_insn_reservation "power10-crypto" 4
(and (eq_attr "type" "crypto")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
; HTM
(define_insn_reservation "power10-htm" 2
(and (eq_attr "type" "htmsimple,htm")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
@@ -536,26 +535,26 @@
(define_insn_reservation "power10-dfp" 12
(and (eq_attr "type" "dfp")
(eq_attr "size" "!128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_power10")
(define_insn_reservation "power10-dfpq" 12
(and (eq_attr "type" "dfp")
(eq_attr "size" "128")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_power10")
; MMA
(define_insn_reservation "power10-mma" 9
(and (eq_attr "type" "mma")
(eq_attr "prefixed" "no")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_any_power10,EXU_super_power10")
(define_insn_reservation "power10-prefixed-mma" 9
(and (eq_attr "type" "mma")
(eq_attr "prefixed" "yes")
- (eq_attr "cpu" "power10,power11,future"))
+ (eq_attr "cpu" "power10,power11"))
"DU_even_power10,EXU_super_power10")
; 4 cycle MMA->MMA latency
(define_bypass 4 "power10-mma,power10-prefixed-mma"
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index d15bb85743c..ebed8b9554a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -449,8 +449,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10");
if ((flags & OPTION_MASK_POWER11) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
- if ((flags & OPTION_MASK_FUTURE) != 0)
- rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 47365534af8..3237a5ada30 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -89,9 +89,6 @@
#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
| OPTION_MASK_POWER11)
-#define ISA_FUTURE_MASKS_SERVER (ISA_POWER11_MASKS_SERVER \
- | OPTION_MASK_FUTURE)
-
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -130,7 +127,6 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
- | OPTION_MASK_FUTURE \
| OPTION_MASK_POWER10 \
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
@@ -266,4 +262,3 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
| ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
-RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index d6c766309aa..4f5af57ae1a 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -68,8 +68,7 @@ enum processor_type
PROCESSOR_CELL,
PROCESSOR_PPCA2,
PROCESSOR_TITAN,
- PROCESSOR_POWER11,
- PROCESSOR_FUTURE
+ PROCESSOR_POWER11
};
diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc
index e74ccf41937..9c8a81172e3 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -965,7 +965,6 @@ expand_compare_loop (rtx operands[])
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
if (bytes_is_const)
max_bytes = 191;
else
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index f009c4e5718..7e5bb6e7658 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -200,6 +200,3 @@ Enum(rs6000_cpu_opt_value) String(rs64) Value(56)
EnumValue
Enum(rs6000_cpu_opt_value) String(power11) Value(57)
-EnumValue
-Enum(rs6000_cpu_opt_value) String(future) Value(58)
-
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2921e72aea8..b718b9cf0bc 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = {
COSTS_N_INSNS (3), /* SF->DF convert */
};
-/* Instruction costs on POWER10/POWER11/FUTURE processors. */
+/* Instruction costs on POWER10/POWER11 processors. */
static const
struct processor_costs power10_cost = {
COSTS_N_INSNS (2), /* mulsi */
@@ -4380,8 +4380,7 @@ rs6000_option_override_internal (bool global_init_p)
if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
{
if (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
else
rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
@@ -4411,7 +4410,6 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_tune != PROCESSOR_POWER9
&& rs6000_tune != PROCESSOR_POWER10
&& rs6000_tune != PROCESSOR_POWER11
- && rs6000_tune != PROCESSOR_FUTURE
&& rs6000_tune != PROCESSOR_PPCA2
&& rs6000_tune != PROCESSOR_CELL
&& rs6000_tune != PROCESSOR_PPC476);
@@ -4427,7 +4425,6 @@ rs6000_option_override_internal (bool global_init_p)
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_PPCE500MC
|| rs6000_tune == PROCESSOR_PPCE500MC64
|| rs6000_tune == PROCESSOR_PPCE5500
@@ -4728,7 +4725,6 @@ rs6000_option_override_internal (bool global_init_p)
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
rs6000_cost = &power10_cost;
break;
@@ -5888,8 +5884,6 @@ rs6000_machine_from_flags (void)
/* Disable the flags that should never influence the .machine selection. */
flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL);
- if ((flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_POWER11_MASKS_SERVER)) != 0)
- return "future";
if ((flags & (ISA_POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
return "power11";
if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
@@ -10139,7 +10133,6 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
case PROCESSOR_POWER9:
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
if (DECIMAL_FLOAT_MODE_P (mode))
return 1;
if (VECTOR_MODE_P (mode))
@@ -18222,8 +18215,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
/* Separate a load from a narrower, dependent store. */
if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& MEM_P (XEXP (PATTERN (insn), 1))
@@ -18263,7 +18255,6 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
|| rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
|| rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_CELL)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0))
@@ -18839,7 +18830,6 @@ rs6000_issue_rate (void)
return 6;
case PROCESSOR_POWER10:
case PROCESSOR_POWER11:
- case PROCESSOR_FUTURE:
return 8;
default:
return 1;
@@ -19555,11 +19545,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
if (rs6000_tune == PROCESSOR_POWER6)
load_store_pendulum = 0;
- /* Do Power10/power11/future dependent reordering. */
+ /* Do Power10/power11 dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE))
+ || rs6000_tune == PROCESSOR_POWER11))
power10_sched_reorder (ready, n_ready - 1);
return rs6000_issue_rate ();
@@ -19583,11 +19572,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
&& recog_memoized (last_scheduled_insn) >= 0)
return power9_sched_reorder2 (ready, *pn_ready - 1);
- /* Do Power10/power11/future dependent reordering. */
+ /* Do Power10/power11 dependent reordering. */
if (last_scheduled_insn
&& (rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE))
+ || rs6000_tune == PROCESSOR_POWER11))
return power10_sched_reorder (ready, *pn_ready - 1);
return cached_can_issue_more;
@@ -22805,8 +22793,7 @@ rs6000_register_move_cost (machine_mode mode,
out to be a nop. */
if (rs6000_tune == PROCESSOR_POWER9
|| rs6000_tune == PROCESSOR_POWER10
- || rs6000_tune == PROCESSOR_POWER11
- || rs6000_tune == PROCESSOR_FUTURE)
+ || rs6000_tune == PROCESSOR_POWER11)
ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
else
ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -24464,7 +24451,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
- { "future", OPTION_MASK_FUTURE, false, false },
{ "power10", OPTION_MASK_POWER10, false, true },
{ "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 79ce1a8cbf1..407cb379a0c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -106,7 +106,6 @@
you make changes here, make them also there. */
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
- mcpu=future: -mfuture; \
mcpu=power11: -mpower11; \
mcpu=power10: -mpower10; \
mcpu=power9: -mpower9; \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index abc809448ad..ea4add5b283 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -351,7 +351,7 @@
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
power4,power5,power6,power7,power8,power9,power10,
- rs64a,mpccore,cell,ppca2,titan,power11,future"
+ rs64a,mpccore,cell,ppca2,titan,power11"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 621ebd65a88..e7a4e4a2ddd 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -584,9 +584,6 @@ Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
mpower11
Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
-mfuture
-Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
-
mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
Generate (do not generate) prefixed memory instructions.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 27d0c8da033..a092d95e8f4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31169,7 +31169,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{power10}, @samp{power11}, @samp{future},
+@samp{power9}, @samp{power10}, @samp{power11},
@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
@samp{rs64}, and @samp{native}.
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