[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

[Michael Meissner]

https://gcc.gnu.org/g:145bc7b00c10cf6e59897aba7f61c3a24c85ca0b

commit 145bc7b00c10cf6e59897aba7f61c3a24c85ca0b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 21 23:49:02 2024 -0400

    Add support for XVRL instruction.
    
    2024-03-21  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/altivec.md (futue_xvrlw): New insn.

Diff:
---
 gcc/config/rs6000/altivec.md | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 4d4c94ff0a0..afe3d72316c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,6 +1883,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*future_xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_FUTURE"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

[Michael Meissner]

https://gcc.gnu.org/g:7200cbd8395cb620028eeb6c6ef003f6064615e2

commit 7200cbd8395cb620028eeb6c6ef003f6064615e2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 22 00:37:34 2024 -0400

    Add support for XVRL instruction.
    
    2024-03-22  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/altivec.md (xvrlw): New insn.

Diff:
---
 gcc/config/rs6000/altivec.md | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 4d4c94ff0a0..bf01af15286 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,6 +1883,20 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; -mcpu=future adds a vector rotate left word variant.  There is no vector
+;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
+;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_FUTURE"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")

[gcc(refs/users/meissner/heads/work163-dmf)] Add support for XVRL instruction.

[Michael Meissner]

https://gcc.gnu.org/g:6ff874d066d523bd6b71e2f944f5740f651ed022

commit 6ff874d066d523bd6b71e2f944f5740f651ed022
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 21 23:39:11 2024 -0400

    Add support for XVRL instruction.
    
    2024-03-21  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/altivec.md (xvrlw): New insn.

Diff:
---
 gcc/config/rs6000/altivec.md | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 4d4c94ff0a0..da5db49d3af 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,6 +1883,17 @@
 }
   [(set_attr "type" "vecperm")])
 
+;; Future cpu adds a vector rotate left word variant
+(define_insn "*xvrlw"
+  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
+  "TARGET_FUTURE"
+  "@
+   vrlw %0,%1,%2
+   xvrlw %x0,%x1,%x2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")