[gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes

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* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22 18:24 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22 18:24 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:0995cf8ede2865c37becd0e8c76ca78a6f64901d

commit 0995cf8ede2865c37becd0e8c76ca78a6f64901d
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 22 14:24:37 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/altivec.md                |  14 ---
 gcc/config/rs6000/constraints.md            |  10 --
 gcc/config/rs6000/predicates.md             |  52 +---------
 gcc/config/rs6000/rs6000-builtin.cc         |  17 ---
 gcc/config/rs6000/rs6000-builtins.def       |  10 --
 gcc/config/rs6000/rs6000-gen-builtins.cc    |  35 +------
 gcc/config/rs6000/rs6000-string.cc          |   1 -
 gcc/config/rs6000/rs6000.cc                 |  40 -------
 gcc/config/rs6000/rs6000.h                  |   1 -
 gcc/config/rs6000/rs6000.md                 | 156 +++-------------------------
 gcc/config/rs6000/rs6000.opt                |   4 -
 gcc/config/rs6000/vsx.md                    | 122 ++++------------------
 gcc/doc/extend.texi                         |  24 -----
 gcc/testsuite/gcc.target/powerpc/lxvrl.c    |  32 ------
 gcc/testsuite/gcc.target/powerpc/subfus-1.c |  32 ------
 gcc/testsuite/gcc.target/powerpc/subfus-2.c |  32 ------
 gcc/testsuite/lib/target-supports.exp       |  12 ---
 17 files changed, 40 insertions(+), 554 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index bf01af15286..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_FUTURE"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4d8d21fd6bb..277a30a8245 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
-(define_constraint "eU"
-  "@internal integer constant that can be loaded with paddis"
-  (and (match_code "const_int")
-       (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
-  "@internal integer constant that can be loaded with paddis + paddi"
-  (and (match_code "const_int")
-       (match_operand 0 "paddis_paddi_operand")))
-
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0b7c0bf4b0f..b325000690b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-    return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-    return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-    return false;
-
-  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
-  if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0)
-    return false;
-
-  return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-    return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-    return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-    return false;
-
-  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
-  if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0)
-    return false;
-
-  return true;
-})
-
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1097,10 +1050,7 @@
   (if_then_else (match_code "const_int")
     (match_test "satisfies_constraint_I (op)
 		 || satisfies_constraint_L (op)
-		 || satisfies_constraint_eI (op)
-		 || satisfies_constraint_eU (op)
-		 || satisfies_constraint_eV (op)")
-
+		 || satisfies_constraint_eI (op)")
     (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 1af38698bf3..976a42a74cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,17 +139,6 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
     case ENB_MMA:
       error ("%qs requires the %qs option", name, "-mmma");
       break;
-    case ENB_FUTURE:
-      error ("%qs requires the %qs option", name, "-mcpu=future");
-      break;
-    case ENB_FUTURE_64:
-      error ("%qs requires the %qs option and either the %qs or %qs option",
-	     name, "-mcpu=future", "-m64", "-mpowerpc64");
-      break;
-    case ENB_DM:
-      error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
-	     "-mdense-math");
-      break;
     default:
     case ENB_ALWAYS:
       gcc_unreachable ();
@@ -205,12 +194,6 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
       return TARGET_HTM;
     case ENB_MMA:
       return TARGET_MMA;
-    case ENB_FUTURE:
-      return TARGET_FUTURE;
-    case ENB_FUTURE_64:
-      return TARGET_FUTURE && TARGET_POWERPC64;
-    case ENB_DM:
-      return TARGET_DENSE_MATH;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 437ab0e09e9..3bc7fed6956 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -139,8 +139,6 @@
 ;   endian   Needs special handling for endianness
 ;   ibmld    Restrict usage to the case when TFmode is IBM-128
 ;   ibm128   Restrict usage to the case where __ibm128 is supported or if ibmld
-;   future   Restrict usage to future instructions
-;   dm       Restrict usage to dense math
 ;
 ; Each attribute corresponds to extra processing required when
 ; the built-in is expanded.  All such special processing should
@@ -4133,11 +4131,3 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
     STXVP nothing {mma,pair}
-
-[future]
-  const signed int __builtin_saturate_subtract32 (signed int, signed int);
-  SAT_SUBSI sat_subsi3 {}
-
-[future-64]
-  const signed long __builtin_saturate_subtract64 (signed long,  signed long);
-  SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc b/gcc/config/rs6000/rs6000-gen-builtins.cc
index acd65d4bd0a..e32d1e2d134 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -233,9 +233,6 @@ enum bif_stanza
  BSTZ_P10,
  BSTZ_P10_64,
  BSTZ_MMA,
- BSTZ_FUTURE,
- BSTZ_FUTURE_64,
- BSTZ_DM,
  NUMBIFSTANZAS
 };
 
@@ -269,10 +266,7 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] =
     { "htm",		BSTZ_HTM	},
     { "power10",	BSTZ_P10	},
     { "power10-64",	BSTZ_P10_64	},
-    { "mma",		BSTZ_MMA	},
-    { "future",		BSTZ_FUTURE	},
-    { "future-64",	BSTZ_FUTURE_64	},
-    { "dm",		BSTZ_DM		},
+    { "mma",		BSTZ_MMA	}
   };
 
 static const char *enable_string[NUMBIFSTANZAS] =
@@ -297,10 +291,7 @@ static const char *enable_string[NUMBIFSTANZAS] =
     "ENB_HTM",
     "ENB_P10",
     "ENB_P10_64",
-    "ENB_MMA",
-    "ENB_FUTURE",
-    "ENB_FUTURE_64",
-    "ENB_DM",
+    "ENB_MMA"
   };
 
 /* Function modifiers provide special handling for const, pure, and fpmath
@@ -404,8 +395,6 @@ struct attrinfo
   bool isendian;
   bool isibmld;
   bool isibm128;
-  bool isfuture;
-  bool isdm;
 };
 
 /* Fields associated with a function prototype (bif or overload).  */
@@ -1488,8 +1477,7 @@ parse_bif_attrs (attrinfo *attrptr)
 	"ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, "
 	"htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, "
 	"mmaint = %d, no32bit = %d, 32bit = %d, cpu = %d, ldstmask = %d, "
-	"lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d,",
-	"future = %d, dm = %d.\n",
+	"lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d.\n",
 	attrptr->isinit, attrptr->isset, attrptr->isextract,
 	attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec,
 	attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr,
@@ -1497,7 +1485,7 @@ parse_bif_attrs (attrinfo *attrptr)
 	attrptr->ismmaint, attrptr->isno32bit, attrptr->is32bit,
 	attrptr->iscpu, attrptr->isldstmask, attrptr->islxvrse,
 	attrptr->islxvrze, attrptr->isendian, attrptr->isibmld,
-	attrptr->isibm128, attrptr->isfuture, attrptr->isdm);
+	attrptr->isibm128);
 #endif
 
   return PC_OK;
@@ -2269,10 +2257,7 @@ write_decls (void)
   fprintf (header_file, "  ENB_HTM,\n");
   fprintf (header_file, "  ENB_P10,\n");
   fprintf (header_file, "  ENB_P10_64,\n");
-  fprintf (header_file, "  ENB_MMA,\n");
-  fprintf (header_file, "  ENB_FUTURE,\n");
-  fprintf (header_file, "  ENB_FUTURE_64,\n");
-  fprintf (header_file, "  ENB_DM\n");
+  fprintf (header_file, "  ENB_MMA\n");
   fprintf (header_file, "};\n\n");
 
   fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n");
@@ -2316,8 +2301,6 @@ write_decls (void)
   fprintf (header_file, "#define bif_endian_bit\t\t(0x00200000)\n");
   fprintf (header_file, "#define bif_ibmld_bit\t\t(0x00400000)\n");
   fprintf (header_file, "#define bif_ibm128_bit\t\t(0x00800000)\n");
-  fprintf (header_file, "#define bif_future_bit\t\t(0x01000000)\n");
-  fprintf (header_file, "#define bif_dm_bit\t\t(0x02000000)\n");
   fprintf (header_file, "\n");
   fprintf (header_file,
 	   "#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n");
@@ -2367,10 +2350,6 @@ write_decls (void)
 	   "#define bif_is_ibmld(x)\t((x).bifattrs & bif_ibmld_bit)\n");
   fprintf (header_file,
 	   "#define bif_is_ibm128(x)\t((x).bifattrs & bif_ibm128_bit)\n");
-  fprintf (header_file,
-	   "#define bif_is_future(x)\t((x).bifattrs & bif_future_bit)\n");
-  fprintf (header_file,
-	   "#define bif_is_dm(x)\t((x).bifattrs & bif_dm_bit)\n");
   fprintf (header_file, "\n");
 
   fprintf (header_file,
@@ -2569,10 +2548,6 @@ write_bif_static_init (void)
 	fprintf (init_file, " | bif_ibmld_bit");
       if (bifp->attrs.isibm128)
 	fprintf (init_file, " | bif_ibm128_bit");
-      if (bifp->attrs.isfuture)
-	fprintf (init_file, " | bif_future_bit");
-      if (bifp->attrs.isdm)
-	fprintf (init_file, " | bif_dm_bit");
       fprintf (init_file, ",\n");
       fprintf (init_file, "      /* restr_opnd */\t{%d, %d, %d},\n",
 	       bifp->proto.restr_opnd[0], bifp->proto.restr_opnd[1],
diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc
index c6737e66cbe..e74ccf41937 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2787,7 +2787,6 @@ expand_block_move (rtx operands[], bool might_overlap)
 
       if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
 	  && TARGET_BLOCK_OPS_VECTOR_PAIR
-	  && TARGET_POWERPC64
 	  && bytes >= 32
 	  && (align >= 256 || !STRICT_ALIGNMENT))
 	{
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b34bd0f0899..573602d0c11 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4307,16 +4307,6 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_PCREL;
     }
 
-
-  /* -mpaddis requires -mcpu=future.  */
-  if (TARGET_PADDIS && !TARGET_FUTURE)
-    {
-      if (OPTION_SET_P (TARGET_PADDIS))
-	error ("%qs requires %qs", "-mpaddis", "-mcpu=future");
-
-      TARGET_PADDIS = 0;
-    }
-
   /* Print the options after updating the defaults.  */
   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
     rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
@@ -6127,17 +6117,6 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
   else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
     return 1;
 
-  /* PADDIS support.  */
-  else if (TARGET_PADDIS && TARGET_POWERPC64
-	   && !IN_RANGE (value >> 32, -1, 0)
-	   && (SIGNED_INTEGER_32BIT_P (value >> 32)))
-    {
-      fprintf (stderr, "=== 0x%lx ===\n", (long)value);
-      return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
-	      ? 1
-	      : 2);
-    }
-
   else if (TARGET_POWERPC64)
     {
       int num_insns = 0;
@@ -6158,14 +6137,6 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
 {
   int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
   int total = 0;
-  if (nregs == 1
-      && TARGET_PADDIS && TARGET_POWERPC64
-      && !IN_RANGE (value >> 32, -1, 0)
-      && SIGNED_INTEGER_32BIT_P (value >> 32))
-    return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
-	    ? 1
-	    : 2);
-
   while (nregs-- > 0)
     {
       HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
@@ -14240,14 +14211,6 @@ print_operand (FILE *file, rtx x, int code)
 	fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
       return;
 
-    case 'B':
-      /* Upper 32-bits of a constant.  */
-      if (!CONST_INT_P (x))
-	output_operand_lossage ("Not a constant.");
-
-      fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32);
-      return;
-
     case 'D':
       /* Like 'J' but get to the GT bit only.  */
       if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
@@ -24782,9 +24745,6 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
   { "speculate-indirect-jumps",
     offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
     offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
-  { "paddis",
-    offsetof (struct gcc_options, x_TARGET_PADDIS),
-    offsetof (struct cl_target_option, x_TARGET_PADDIS), },
 };
 
 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 693de2ba72c..67ef3d3a7d0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2495,7 +2495,6 @@ typedef struct GTY(()) machine_function
 	    (HOST_WIDE_INT_1 << ((N)-1)) - 1)
 
 #define SIGNED_INTEGER_16BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 16)
-#define SIGNED_INTEGER_32BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 32)
 #define SIGNED_INTEGER_34BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 34)
 
 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f96a228d1ba..2ccd83c9092 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -357,7 +357,7 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,paddis"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
   (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -405,11 +405,6 @@
      (and (eq_attr "isa" "p10")
 	  (match_test "TARGET_POWER10"))
      (const_int 1)
-
-     (and (eq_attr "isa" "paddis")
-	  (match_test "TARGET_PADDIS"))
-     (const_int 1)
-
     ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor
@@ -1815,42 +1810,17 @@
 })
 
 (define_insn "*add<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r,r,b")
-	(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b,b,b")
-		  (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))]
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+	(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")
+		  (match_operand:GPR 2 "add_operand" "r,I,L,eI")))]
   ""
   "@
    add %0,%1,%2
    addi %0,%1,%2
    addis %0,%1,%v2
-   addi %0,%1,%2
-   paddis %0,%1,%B2
-   #"
+   addi %0,%1,%2"
   [(set_attr "type" "add")
-   (set_attr "isa" "*,*,*,p10,paddis,paddis")
-   (set_attr "length" "*,*,*,*,12,24")
-   (set_attr "prefixed" "*,*,*,*,yes,yes")
-   (set_attr "maybe_prefixed" "*,*,*,*,no,no")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand")
-		 (match_operand:DI 2 "paddis_paddi_operand")))]
-  "TARGET_PADDIS && TARGET_POWERPC64"
-  [(set (match_dup 3)
-	(plus:DI (match_dup 1)
-		 (match_dup 4)))
-   (set (match_dup 0)
-	(plus:DI (match_dup 3)
-		 (match_dup 5)))]
-{
-  HOST_WIDE_INT value = INTVAL (operands[2]);
-  operands[3] = (can_create_pseudo_p ()
-		 ? gen_reg_rtx (DImode)
-		 : operands[0]);
-  operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
-  operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
+   (set_attr "isa" "*,*,*,p10")])
 
 (define_insn "*addsi3_high"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -9865,7 +9835,7 @@
   DONE;
 })
 
-;;	   GPR store   GPR load    GPR move    GPR paddis   GPR paddis+paddi
+;;	   GPR store   GPR load    GPR move
 ;;	   GPR li      GPR lis     GPR pli     GPR #
 ;;	   FPR store   FPR load    FPR move
 ;;	   AVX store   AVX store   AVX load    AVX load    VSX move
@@ -9875,7 +9845,7 @@
 ;;	   VSX->GPR    GPR->VSX
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-	  "=YZ,        r,          r,          r,          b,
+	  "=YZ,        r,          r,
 	   r,          r,          r,          r,
 	   m,          ^d,         ^d,
 	   wY,         Z,          $v,         $v,         ^wa,
@@ -9884,7 +9854,7 @@
 	   r,          *h,         *h,
 	   ?r,         ?wa")
 	(match_operand:DI 1 "input_operand"
-	  "r,          YZ,         r,          eU,         eV,
+	  "r,          YZ,         r,
 	   I,          L,          eI,         nF,
 	   ^d,         m,          ^d,
 	   ^v,         $v,         wY,         Z,          ^wa,
@@ -9899,8 +9869,6 @@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
    mr %0,%1
-   paddis %0,0,%B1
-   #
    li %0,%1
    lis %0,%v1
    li %0,%1
@@ -9926,7 +9894,7 @@
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
   [(set_attr "type"
-	  "store,      load,       *,          *,          *,
+	  "store,      load,       *,
 	   *,          *,          *,          *,
 	   fpstore,    fpload,     fpsimple,
 	   fpstore,    fpstore,    fpload,     fpload,     veclogical,
@@ -9936,7 +9904,7 @@
 	   mfvsr,      mtvsr")
    (set_attr "size" "64")
    (set_attr "length"
-	  "*,          *,          *,          12,         24,
+	  "*,          *,          *,
 	   *,          *,          *,          20,
 	   *,          *,          *,
 	   *,          *,          *,          *,          *,
@@ -9945,32 +9913,14 @@
 	   *,          *,          *,
 	   *,          *")
    (set_attr "isa"
-	  "*,          *,          *,          paddis,     paddis,
+	  "*,          *,          *,
 	   *,          *,          p10,        *,
 	   *,          *,          *,
 	   p9v,        p7v,        p9v,        p7v,        *,
 	   p9v,        p9v,        p7v,        *,          *,
 	   p7v,        p7v,
 	   *,          *,          *,
-	   p8v,        p8v")
-   (set_attr "prefixed"
-	  "*,          *,          *,          yes,        yes,
-	   *,          *,          *,          *,
-	   *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,
-	   *,          *,          *,
-	   *,          *")
-   (set_attr "maybe_prefixed"
-	  "*,          *,          *,          no,         no,
-	   *,          *,          *,          *,
-	   *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,
-	   *,          *,          *,
-	   *,          *")])
+	   p8v,        p8v")])
 
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.
@@ -9988,26 +9938,6 @@
 		(match_dup 1)))]
   "")
 
-;; Split a constant that can be generated by a paddis and paddi into 2
-;; instructions.
-(define_split
-  [(set (match_operand:DI 0 "int_reg_operand")
-	(match_operand:DI 1 "paddis_paddi_operand"))]
-  "TARGET_PADDIS && TARGET_POWERPC64"
-  [(set (match_dup 2)
-	(match_dup 3))
-   (set (match_dup 0)
-	(plus:DI (match_dup 2)
-		 (match_dup 4)))]
-{
-  HOST_WIDE_INT value = INTVAL (operands[1]);
-  operands[2] = (can_create_pseudo_p ()
-		 ? gen_reg_rtx (DImode)
-		 : operands[0]);
-  operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
-  operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
-
 ;; Split a load of a large constant into the appropriate five-instruction
 ;; sequence.  Handle anything in a constant number of insns.
 ;; When non-easy constants can go in the TOC, this should use
@@ -15892,66 +15822,6 @@
 }
   [(set_attr "type" "load")])
 \f
-;; Signed saturation.
-
-;; The subfus instruction is defined as: SUBFUS RT,L,RA,RB.  The extended
-;; mnemonic that we use (subdus and subwus) has the arguments RA and RB
-;; reversed (so it becomes a subtract instead of subtract from).
-
-(define_insn "sat_sub<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-		      (match_operand:GPR 2 "gpc_reg_operand" "r")))]
-  "TARGET_FUTURE"
-  "sub<wd>us %0,%1,%2"
-  [(set_attr "type" "add")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-				  (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:GPR 0 "=r,r"))]
-  "TARGET_FUTURE"
-  "@
-   sub<wd>us. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "add")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot2"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-				  (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))]
-  "TARGET_FUTURE"
-  "@
-   sub<wd>us. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "add")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-\f
 
 (include "sync.md")
 (include "vector.md")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index cfefe65afbe..621ebd65a88 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -603,10 +603,6 @@ mmma
 Target Mask(MMA) Var(rs6000_isa_flags)
 Generate (do not generate) MMA instructions.
 
-mpaddis
-Target Undocumented Var(TARGET_PADDIS) Save
-Generate (do not generate) the paddis instruction.
-
 mrelative-jumptables
 Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
 
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9520191e613..f135fa079bd 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5629,32 +5629,20 @@
   DONE;
 })
 
-;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
-;; explicit shift left into a pseudo.
+;; Load VSX Vector with Length
 (define_expand "lxvl"
-  [(use (match_operand:V16QI 0 "vsx_register_operand"))
-   (use (match_operand:DI 1 "gpc_reg_operand"))
-   (use (match_operand:DI 2 "gpc_reg_operand"))]
+  [(set (match_dup 3)
+        (ashift:DI (match_operand:DI 2 "register_operand")
+                   (const_int 56)))
+   (set (match_operand:V16QI 0 "vsx_register_operand")
+	(unspec:V16QI
+	 [(match_operand:DI 1 "gpc_reg_operand")
+          (mem:V16QI (match_dup 1))
+	  (match_dup 3)]
+	 UNSPEC_LXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
-  rtx len;
-
-  if (TARGET_FUTURE)
-    len = shift_len;
-  else
-    {
-      len = gen_reg_rtx (DImode);
-      emit_insn (gen_rtx_SET (len, shift_len));
-    }
-
-  rtx dest = operands[0];
-  rtx addr = operands[1];
-  rtx mem = gen_rtx_MEM (V16QImode, addr);
-  rtvec rv = gen_rtvec (3, addr, mem, len);
-  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
-  emit_insn (gen_rtx_SET (dest, lxvl));
-  DONE;
+  operands[3] = gen_reg_rtx (DImode);
 })
 
 (define_insn "*lxvl"
@@ -5678,34 +5666,6 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
-;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
-;; define_expand for lxvl will already incorporate the shift in generating the
-;; insn.  The lxvll buitl-in function required the user to have already done
-;; the shift.  Defining lxvrll this way, will optimize cases where the user has
-;; done the shift immediately before the built-in.
-(define_insn "*lxvrl"
-  [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-	(unspec:V16QI
-	 [(match_operand:DI 1 "gpc_reg_operand" "b")
-	  (mem:V16QI (match_dup 1))
-	  (ashift:DI (match_operand:DI 2 "register_operand" "r")
-		     (const_int 56))]
-	 UNSPEC_LXVL))]
-  "TARGET_FUTURE && TARGET_64BIT"
-  "lxvrl %x0,%1,%2"
-  [(set_attr "type" "vecload")])
-
-(define_insn "*lxvrll"
-  [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-	(unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")
-                       (mem:V16QI (match_dup 1))
-		       (ashift:DI (match_operand:DI 2 "register_operand" "r")
-				  (const_int 56))]
-		      UNSPEC_LXVLL))]
-  "TARGET_FUTURE"
-  "lxvrll %x0,%1,%2"
-  [(set_attr "type" "vecload")])
-
 ;; Expand for builtin xl_len_r
 (define_expand "xl_len_r"
   [(match_operand:V16QI 0 "vsx_register_operand")
@@ -5737,29 +5697,18 @@
 
 ;; Store VSX Vector with Length
 (define_expand "stxvl"
-  [(use (match_operand:V16QI 0 "vsx_register_operand"))
-   (use (match_operand:DI 1 "gpc_reg_operand"))
-   (use (match_operand:DI 2 "gpc_reg_operand"))]
+  [(set (match_dup 3)
+	(ashift:DI (match_operand:DI 2 "register_operand")
+		   (const_int 56)))
+   (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand"))
+	(unspec:V16QI
+	 [(match_operand:V16QI 0 "vsx_register_operand")
+	  (mem:V16QI (match_dup 1))
+	  (match_dup 3)]
+	 UNSPEC_STXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
-  rtx len;
-
-  if (TARGET_FUTURE)
-    len = shift_len;
-  else
-    {
-      len = gen_reg_rtx (DImode);
-      emit_insn (gen_rtx_SET (len, shift_len));
-    }
-
-  rtx src = operands[0];
-  rtx addr = operands[1];
-  rtx mem = gen_rtx_MEM (V16QImode, addr);
-  rtvec rv = gen_rtvec (3, src, mem, len);
-  rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL);
-  emit_insn (gen_rtx_SET (mem, stxvl));
-  DONE;
+  operands[3] = gen_reg_rtx (DImode);
 })
 
 ;; Define optab for vector access with length vectorization exploitation.
@@ -5803,35 +5752,6 @@
   "stxvl %x0,%1,%2"
   [(set_attr "type" "vecstore")])
 
-;; For stxvrl and stxvrll, use the combiner to eliminate the shift.  The
-;; define_expand for stxvl will already incorporate the shift in generating the
-;; insn.  The stxvll buitl-in function required the user to have already done
-;; the shift.  Defining stxvrll this way, will optimize cases where the user
-;; has done the shift immediately before the built-in.
-
-(define_insn "*stxvrl"
-  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
-	(unspec:V16QI
-	 [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-	  (mem:V16QI (match_dup 1))
-	  (ashift:DI (match_operand:DI 2 "register_operand" "r")
-		     (const_int 56))]
-	 UNSPEC_STXVL))]
-  "TARGET_FUTURE && TARGET_64BIT"
-  "stxvrl %x0,%1,%2"
-  [(set_attr "type" "vecstore")])
-
-(define_insn "*stxvrll"
-  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
-	(unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-		       (mem:V16QI (match_dup 1))
-		       (ashift:DI (match_operand:DI 2 "register_operand" "r")
-				  (const_int 56))]
-	              UNSPEC_STXVLL))]
-  "TARGET_FUTURE"
-  "stxvrll %x0,%1,%2"
-  [(set_attr "type" "vecstore")])
-
 ;; Expand for builtin xst_len_r
 (define_expand "xst_len_r"
   [(match_operand:V16QI 0 "vsx_register_operand" "=wa")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 713e7ee96c0..7b54a241a7b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20963,7 +20963,6 @@ Reverse the bit order of a 64-bit unsigned integer.
 * Basic PowerPC Built-in Functions Available on ISA 2.07::
 * Basic PowerPC Built-in Functions Available on ISA 3.0::
 * Basic PowerPC Built-in Functions Available on ISA 3.1::
-* Basic Built-in Functions that may be available on future PowerPCs::
 @end menu
 
 This section describes PowerPC built-in functions that do not require
@@ -21615,29 +21614,6 @@ ISA 3.1 @code{stxvrbx}, @code{stxvrhx}, @code{stxvrwx}, and @code{stxvrdx}
 instructions.
 @enddefbuiltin
 
-@node Basic Built-in Functions that may be available on future PowerPCs
-@subsubsection Potential future PowerPC Built-in Functions
-
-The built-in functions described in this section may be available on
-future PowerPC processors.  At present, these built-ins exist to
-allowing testing of new instructions.  There is no guarantee that
-these instructions will actually be implemented.
-
-The following built-in functions are available on Linux 64-bit systems
-that use a potential future instruction set (@option{-mcpu=future}):
-
-@table @code
-@item int __builtin_saturate_subtract32 (int, int)
-Subtract the second operand from the first operand.  If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-
-@item long __builtin_saturate_subtract64 (long, long)
-Subtract the second operand from the first operand.  If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-@end table
-
 @node PowerPC AltiVec/VSX Built-in Functions
 @subsection PowerPC AltiVec/VSX Built-in Functions
 
diff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c b/gcc/testsuite/gcc.target/powerpc/lxvrl.c
deleted file mode 100644
index 71854c50c91..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/lxvrl.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the lxvrl and stxvrl instructions are generated for
-   -mcpu=future on memory copy operations.  */
-
-#ifndef VSIZE
-#define VSIZE 2
-#endif
-
-#ifndef LSIZE
-#define LSIZE 5
-#endif
-
-struct foo {
-  vector unsigned char vc[VSIZE];
-  unsigned char leftover[LSIZE];
-};
-
-void memcpy_ptr (struct foo *p, struct foo *q)
-{
-  __builtin_memcpy ((void *) p,		/* lxvrl and stxvrl.  */
-		    (void *) q,
-		    (sizeof (vector unsigned char) * VSIZE) + LSIZE);
-}
-
-/* { dg-final { scan-assembler     {\mlxvrl\M}  } } */
-/* { dg-final { scan-assembler     {\mstxvrl\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvl\M}   } } */
-/* { dg-final { scan-assembler-not {\mstxvl\M}  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-1.c b/gcc/testsuite/gcc.target/powerpc/subfus-1.c
deleted file mode 100644
index 535e7f8483d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-1.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 32-bit
-   subtracts.  */
-
-int do_sat_int  (int  a, int  b)
-{
-  return __builtin_saturate_subtract32 (a, b);		/* subwus  */
-}
-
-int do_sat_int_dot  (int  a, int  b, int  *p)
-{
-  int  r = __builtin_saturate_subtract32 (a, b);	/* subwus.  */
-  if (r == 0)
-    *p = 0;
-
-  return r;
-}
-
-void do_sat_int_dot2  (int  a, int  b, int  *p, int *q)
-{
-  if (__builtin_saturate_subtract32 (a, b))		/* subwus.  */
-    *p = 0;
-
-  *q = a + b;
-  return;
-}
-
-/* { dg-final { scan-assembler     {\msubwus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-2.c b/gcc/testsuite/gcc.target/powerpc/subfus-2.c
deleted file mode 100644
index b68e66dd2b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-2.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 64-bit
-   subtracts.  */
-
-long do_sat_long  (long  a, long  b)
-{
-  return __builtin_saturate_subtract64 (a, b);		/* subwus  */
-}
-
-long do_sat_long_dot  (long  a, long  b, long  *p)
-{
-  long  r = __builtin_saturate_subtract64 (a, b);	/* subwus.  */
-  if (r == 0)
-    *p = 0;
-
-  return r;
-}
-
-void do_sat_long_dot2  (long  a, long  b, long  *p, long *q)
-{
-  if (__builtin_saturate_subtract64 (a, b))		/* subwus.  */
-    *p = 0;
-
-  *q = a + b;
-  return;
-}
-
-/* { dg-final { scan-assembler     {\msubdus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M}   } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 6b87d88aa75..14b3737eecf 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7121,18 +7121,6 @@ proc check_effective_target_power11_ok { } {
     }
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the saturating subtract instruction.
-proc check_effective_target_powerpc_future_ok { } {
-       return [check_no_compiler_messages powerpc_future_ok object {
-           #ifndef _ARCH_PWR_FUTURE
-           #error "-mcpu=future is not supported"
-           #else
-           int dummy;
-           #endif
-       } "-mcpu=future"]
-}
-
 # Return 1 if this is a PowerPC target supporting -mcpu=future which enables
 # the dense math operations.
 proc check_effective_target_powerpc_dense_math_ok { } {

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22 19:29 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22 19:29 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:9685bb23ef366fdf4125c52edf5d19fe82a6e276

commit 9685bb23ef366fdf4125c52edf5d19fe82a6e276
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 22 15:29:53 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/aix71.h                 |  1 -
 gcc/config/rs6000/aix72.h                 |  1 -
 gcc/config/rs6000/aix73.h                 |  1 -
 gcc/config/rs6000/altivec.md              | 14 -----
 gcc/config/rs6000/constraints.md          | 10 ----
 gcc/config/rs6000/predicates.md           | 52 +----------------
 gcc/config/rs6000/rs6000-c.cc             |  2 -
 gcc/config/rs6000/rs6000-cpus.def         |  5 --
 gcc/config/rs6000/rs6000-tables.opt       |  3 -
 gcc/config/rs6000/rs6000.cc               | 26 ---------
 gcc/config/rs6000/rs6000.h                |  5 --
 gcc/config/rs6000/rs6000.md               | 96 +++++--------------------------
 gcc/config/rs6000/rs6000.opt              |  4 --
 gcc/testsuite/gcc.target/powerpc/paddis.c | 24 --------
 gcc/testsuite/gcc.target/powerpc/xvrlw.c  | 34 -----------
 gcc/testsuite/lib/target-supports.exp     | 13 -----
 16 files changed, 14 insertions(+), 277 deletions(-)

diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 34bbad65dbe..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index f5e66084553..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1140f0f6098..2bd6b4bb3c4 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 87fd3c5f3ef..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_FUTURE2"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4d8d21fd6bb..277a30a8245 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
-(define_constraint "eU"
-  "@internal integer constant that can be loaded with paddis"
-  (and (match_code "const_int")
-       (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
-  "@internal integer constant that can be loaded with paddis + paddi"
-  (and (match_code "const_int")
-       (match_operand 0 "paddis_paddi_operand")))
-
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0b7c0bf4b0f..b325000690b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-    return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-    return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-    return false;
-
-  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
-  if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0)
-    return false;
-
-  return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-    return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-    return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-    return false;
-
-  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
-  if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0)
-    return false;
-
-  return true;
-})
-
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1097,10 +1050,7 @@
   (if_then_else (match_code "const_int")
     (match_test "satisfies_constraint_I (op)
 		 || satisfies_constraint_L (op)
-		 || satisfies_constraint_eI (op)
-		 || satisfies_constraint_eU (op)
-		 || satisfies_constraint_eV (op)")
-
+		 || satisfies_constraint_eI (op)")
     (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index f0461e5817a..acd44058876 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -451,8 +451,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_FUTURE) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
-  if ((flags & OPTION_MASK_FUTURE2) != 0)
-    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE2");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index fee97c96197..4ddba142e44 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -93,9 +93,6 @@
 				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_FUTURE)
 
-#define ISA_FUTURE2_MASKS_SERVER (ISA_FUTURE_MASKS_SERVER		\
-				  | OPTION_MASK_FUTURE2)
-
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS	(OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
@@ -136,7 +133,6 @@
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
 				 | OPTION_MASK_FPRND			\
 				 | OPTION_MASK_FUTURE			\
-				 | OPTION_MASK_FUTURE2			\
 				 | OPTION_MASK_POWER10			\
 				 | OPTION_MASK_POWER11			\
 				 | OPTION_MASK_P10_FUSION		\
@@ -273,4 +269,3 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
 RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
 RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
-RS6000_CPU ("future2", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE2_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 291e295331e..f009c4e5718 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -203,6 +203,3 @@ Enum(rs6000_cpu_opt_value) String(power11) Value(57)
 EnumValue
 Enum(rs6000_cpu_opt_value) String(future) Value(58)
 
-EnumValue
-Enum(rs6000_cpu_opt_value) String(future2) Value(59)
-
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 963c42df3d7..573602d0c11 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4307,7 +4307,6 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_PCREL;
     }
 
-
   /* Print the options after updating the defaults.  */
   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
     rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
@@ -6118,14 +6117,6 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
   else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
     return 1;
 
-  /* PADDIS support.  */
-  else if (TARGET_PADDIS && TARGET_POWERPC64
-	   && !IN_RANGE (value >> 32, -1, 0)
-	   && (SIGNED_INTEGER_32BIT_P (value >> 32)))
-    return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
-	    ? 1
-	    : 2);
-
   else if (TARGET_POWERPC64)
     {
       int num_insns = 0;
@@ -6146,14 +6137,6 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
 {
   int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
   int total = 0;
-  if (nregs == 1
-      && TARGET_PADDIS && TARGET_POWERPC64
-      && !IN_RANGE (value >> 32, -1, 0)
-      && SIGNED_INTEGER_32BIT_P (value >> 32))
-    return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
-	    ? 1
-	    : 2);
-
   while (nregs-- > 0)
     {
       HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
@@ -14228,14 +14211,6 @@ print_operand (FILE *file, rtx x, int code)
 	fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
       return;
 
-    case 'B':
-      /* Upper 32-bits of a constant.  */
-      if (!CONST_INT_P (x))
-	output_operand_lossage ("Not a constant.");
-
-      fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32);
-      return;
-
     case 'D':
       /* Like 'J' but get to the GT bit only.  */
       if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
@@ -24668,7 +24643,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "float128-hardware",	OPTION_MASK_FLOAT128_HW,	false, true  },
   { "fprnd",			OPTION_MASK_FPRND,		false, true  },
   { "future",			OPTION_MASK_FUTURE,		false, false },
-  { "future2",			OPTION_MASK_FUTURE2,		false, false },
   { "power10",			OPTION_MASK_POWER10,		false, true  },
   { "power11",			OPTION_MASK_POWER11,		false, false },
   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 37afa67f184..67ef3d3a7d0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -106,7 +106,6 @@
    you make changes here, make them also there.  */
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpower11; \
   mcpu=power10: -mpower10; \
@@ -574,9 +573,6 @@ extern int rs6000_vector_align[];
    below.  */
 #define RS6000_FN_TARGET_INFO_HTM 1
 
-/* Whether we have PADDIS support.  */
-#define TARGET_PADDIS			TARGET_FUTURE2
-
 /* Whether the various reciprocal divide/square root estimate instructions
    exist, and whether we should automatically generate code for the instruction
    by default.  */
@@ -2499,7 +2495,6 @@ typedef struct GTY(()) machine_function
 	    (HOST_WIDE_INT_1 << ((N)-1)) - 1)
 
 #define SIGNED_INTEGER_16BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 16)
-#define SIGNED_INTEGER_32BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 32)
 #define SIGNED_INTEGER_34BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 34)
 
 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f96a228d1ba..6fffc0db613 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -357,7 +357,7 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,paddis"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
   (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -405,11 +405,6 @@
      (and (eq_attr "isa" "p10")
 	  (match_test "TARGET_POWER10"))
      (const_int 1)
-
-     (and (eq_attr "isa" "paddis")
-	  (match_test "TARGET_PADDIS"))
-     (const_int 1)
-
     ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor
@@ -1815,42 +1810,17 @@
 })
 
 (define_insn "*add<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r,r,b")
-	(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b,b,b")
-		  (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))]
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+	(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")
+		  (match_operand:GPR 2 "add_operand" "r,I,L,eI")))]
   ""
   "@
    add %0,%1,%2
    addi %0,%1,%2
    addis %0,%1,%v2
-   addi %0,%1,%2
-   paddis %0,%1,%B2
-   #"
+   addi %0,%1,%2"
   [(set_attr "type" "add")
-   (set_attr "isa" "*,*,*,p10,paddis,paddis")
-   (set_attr "length" "*,*,*,*,12,24")
-   (set_attr "prefixed" "*,*,*,*,yes,yes")
-   (set_attr "maybe_prefixed" "*,*,*,*,no,no")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand")
-		 (match_operand:DI 2 "paddis_paddi_operand")))]
-  "TARGET_PADDIS && TARGET_POWERPC64"
-  [(set (match_dup 3)
-	(plus:DI (match_dup 1)
-		 (match_dup 4)))
-   (set (match_dup 0)
-	(plus:DI (match_dup 3)
-		 (match_dup 5)))]
-{
-  HOST_WIDE_INT value = INTVAL (operands[2]);
-  operands[3] = (can_create_pseudo_p ()
-		 ? gen_reg_rtx (DImode)
-		 : operands[0]);
-  operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
-  operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
+   (set_attr "isa" "*,*,*,p10")])
 
 (define_insn "*addsi3_high"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -9865,7 +9835,7 @@
   DONE;
 })
 
-;;	   GPR store   GPR load    GPR move    GPR paddis   GPR paddis+paddi
+;;	   GPR store   GPR load    GPR move
 ;;	   GPR li      GPR lis     GPR pli     GPR #
 ;;	   FPR store   FPR load    FPR move
 ;;	   AVX store   AVX store   AVX load    AVX load    VSX move
@@ -9875,7 +9845,7 @@
 ;;	   VSX->GPR    GPR->VSX
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-	  "=YZ,        r,          r,          r,          b,
+	  "=YZ,        r,          r,
 	   r,          r,          r,          r,
 	   m,          ^d,         ^d,
 	   wY,         Z,          $v,         $v,         ^wa,
@@ -9884,7 +9854,7 @@
 	   r,          *h,         *h,
 	   ?r,         ?wa")
 	(match_operand:DI 1 "input_operand"
-	  "r,          YZ,         r,          eU,         eV,
+	  "r,          YZ,         r,
 	   I,          L,          eI,         nF,
 	   ^d,         m,          ^d,
 	   ^v,         $v,         wY,         Z,          ^wa,
@@ -9899,8 +9869,6 @@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
    mr %0,%1
-   paddis %0,0,%B1
-   #
    li %0,%1
    lis %0,%v1
    li %0,%1
@@ -9926,7 +9894,7 @@
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
   [(set_attr "type"
-	  "store,      load,       *,          *,          *,
+	  "store,      load,       *,
 	   *,          *,          *,          *,
 	   fpstore,    fpload,     fpsimple,
 	   fpstore,    fpstore,    fpload,     fpload,     veclogical,
@@ -9936,7 +9904,7 @@
 	   mfvsr,      mtvsr")
    (set_attr "size" "64")
    (set_attr "length"
-	  "*,          *,          *,          12,         24,
+	  "*,          *,          *,
 	   *,          *,          *,          20,
 	   *,          *,          *,
 	   *,          *,          *,          *,          *,
@@ -9945,32 +9913,14 @@
 	   *,          *,          *,
 	   *,          *")
    (set_attr "isa"
-	  "*,          *,          *,          paddis,     paddis,
+	  "*,          *,          *,
 	   *,          *,          p10,        *,
 	   *,          *,          *,
 	   p9v,        p7v,        p9v,        p7v,        *,
 	   p9v,        p9v,        p7v,        *,          *,
 	   p7v,        p7v,
 	   *,          *,          *,
-	   p8v,        p8v")
-   (set_attr "prefixed"
-	  "*,          *,          *,          yes,        yes,
-	   *,          *,          *,          *,
-	   *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,
-	   *,          *,          *,
-	   *,          *")
-   (set_attr "maybe_prefixed"
-	  "*,          *,          *,          no,         no,
-	   *,          *,          *,          *,
-	   *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,
-	   *,          *,          *,
-	   *,          *")])
+	   p8v,        p8v")])
 
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.
@@ -9988,26 +9938,6 @@
 		(match_dup 1)))]
   "")
 
-;; Split a constant that can be generated by a paddis and paddi into 2
-;; instructions.
-(define_split
-  [(set (match_operand:DI 0 "int_reg_operand")
-	(match_operand:DI 1 "paddis_paddi_operand"))]
-  "TARGET_PADDIS && TARGET_POWERPC64"
-  [(set (match_dup 2)
-	(match_dup 3))
-   (set (match_dup 0)
-	(plus:DI (match_dup 2)
-		 (match_dup 4)))]
-{
-  HOST_WIDE_INT value = INTVAL (operands[1]);
-  operands[2] = (can_create_pseudo_p ()
-		 ? gen_reg_rtx (DImode)
-		 : operands[0]);
-  operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
-  operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
-
 ;; Split a load of a large constant into the appropriate five-instruction
 ;; sequence.  Handle anything in a constant number of insns.
 ;; When non-easy constants can go in the TOC, this should use
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 97120a0b64b..621ebd65a88 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -587,10 +587,6 @@ Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpowe
 mfuture
 Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
 
-;; Possible future bits beyound -mcpu=future
-mfuture2
-Target Undocumented Mask(FUTURE2) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture2>)
-
 mprefixed
 Target Mask(PREFIXED) Var(rs6000_isa_flags)
 Generate (do not generate) prefixed memory instructions.
diff --git a/gcc/testsuite/gcc.target/powerpc/paddis.c b/gcc/testsuite/gcc.target/powerpc/paddis.c
deleted file mode 100644
index 09c461b8e06..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/paddis.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future2 -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
-   Altivec registers is generated.  */
-
-#include <stddef.h>
-
-size_t
-prefix_addis_addi (size_t x)
-{
-  return x + 0x1234000056789ABCUL;
-}
-
-size_t
-prefix_addis (size_t x)
-{
-  return x + 0x123400000000000UL;
-}
-
-/* { dg-final { scan-assembler-times {\mpaddis\M} 2  } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M}  1  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/xvrlw.c b/gcc/testsuite/gcc.target/powerpc/xvrlw.c
deleted file mode 100644
index f0a28a8a430..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/xvrlw.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
-   Altivec registers is generated.  */
-
-#include <altivec.h>
-
-typedef vector unsigned int  v4si_t;
-
-v4si_t
-rotl_v4si_scalar (v4si_t x, unsigned long n)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return (x << n) | (x >> (32 - n));
-}
-
-v4si_t
-rotr_v4si_scalar (v4si_t x, unsigned long n)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return (x >> n) | (x << (32 - n));
-}
-
-v4si_t
-rotl_v4si_vector (v4si_t x, v4si_t y)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return vec_rl (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mxvrl\M} 3  } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 7f4617f27f2..9e765e21b1d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7133,19 +7133,6 @@ proc check_effective_target_powerpc_future_ok { } {
        } "-mcpu=future"]
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=future2 which enables
-# potential instructins beyond -mcpu=future.  Note, the assembler may not
-# have support for these instructions.
-proc check_effective_target_powerpc_future2_ok { } {
-       return [check_no_compiler_messages powerpc_future2_ok assembly {
-           #ifndef _ARCH_PWR_FUTURE2
-           #error "-mcpu=future2 is not supported"
-           #else
-           int dummy;
-           #endif
-       } "-mcpu=future2"]
-}
-
 # Return 1 if this is a PowerPC target supporting -mcpu=future which enables
 # the dense math operations.
 proc check_effective_target_powerpc_dense_math_ok { } {

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22 19:18 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22 19:18 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:6dcd642875105c6bc8a11ced11e6e5a766472dcb

commit 6dcd642875105c6bc8a11ced11e6e5a766472dcb
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 22 15:18:30 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/aix71.h                   |   1 -
 gcc/config/rs6000/aix72.h                   |   1 -
 gcc/config/rs6000/aix73.h                   |   1 -
 gcc/config/rs6000/altivec.md                |  14 ---
 gcc/config/rs6000/constraints.md            |  10 --
 gcc/config/rs6000/predicates.md             |  52 +---------
 gcc/config/rs6000/rs6000-builtin.cc         |  17 ---
 gcc/config/rs6000/rs6000-builtins.def       |  10 --
 gcc/config/rs6000/rs6000-c.cc               |   2 -
 gcc/config/rs6000/rs6000-cpus.def           |   5 -
 gcc/config/rs6000/rs6000-gen-builtins.cc    |  35 +------
 gcc/config/rs6000/rs6000-string.cc          |   1 -
 gcc/config/rs6000/rs6000-tables.opt         |   3 -
 gcc/config/rs6000/rs6000.cc                 |  25 -----
 gcc/config/rs6000/rs6000.h                  |   5 -
 gcc/config/rs6000/rs6000.md                 | 156 +++-------------------------
 gcc/config/rs6000/rs6000.opt                |   4 -
 gcc/config/rs6000/vsx.md                    | 122 ++++------------------
 gcc/doc/extend.texi                         |  24 -----
 gcc/testsuite/gcc.target/powerpc/lxvrl.c    |  32 ------
 gcc/testsuite/gcc.target/powerpc/paddis.c   |  24 -----
 gcc/testsuite/gcc.target/powerpc/subfus-1.c |  32 ------
 gcc/testsuite/gcc.target/powerpc/subfus-2.c |  32 ------
 gcc/testsuite/gcc.target/powerpc/xvrlw.c    |  34 ------
 gcc/testsuite/lib/target-supports.exp       |  25 -----
 25 files changed, 40 insertions(+), 627 deletions(-)

diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 34bbad65dbe..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,7 +79,6 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index f5e66084553..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,7 +79,6 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index 1140f0f6098..2bd6b4bb3c4 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,7 +79,6 @@ do {									\
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpwr11; \
   mcpu=power10: -mpwr10; \
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 87fd3c5f3ef..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_FUTURE2"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4d8d21fd6bb..277a30a8245 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
-(define_constraint "eU"
-  "@internal integer constant that can be loaded with paddis"
-  (and (match_code "const_int")
-       (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
-  "@internal integer constant that can be loaded with paddis + paddi"
-  (and (match_code "const_int")
-       (match_operand 0 "paddis_paddi_operand")))
-
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0b7c0bf4b0f..b325000690b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
   return SIGNED_INTEGER_34BIT_P (INTVAL (op));
 })
 
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-    return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-    return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-    return false;
-
-  /* If the bottom 32-bits are non-zero, paddis can't handle it.  */
-  if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0)
-    return false;
-
-  return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
-  (match_code "const_int")
-{
-  if (!TARGET_PADDIS && TARGET_POWERPC64)
-    return 0;
-
-  /* If addi, addis, or paddi can handle the number, don't return true.  */
-  HOST_WIDE_INT value = INTVAL (op);
-  if (SIGNED_INTEGER_34BIT_P (value))
-    return false;
-
-  /* If the number is too large for padds, return false.  */
-  if (!SIGNED_INTEGER_32BIT_P (value >> 32))
-    return false;
-
-  /* If the bottom 32-bits are zero, we can use paddis alone to handle it.  */
-  if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0)
-    return false;
-
-  return true;
-})
-
 ;; Return 1 if op is a register that is not special.
 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1097,10 +1050,7 @@
   (if_then_else (match_code "const_int")
     (match_test "satisfies_constraint_I (op)
 		 || satisfies_constraint_L (op)
-		 || satisfies_constraint_eI (op)
-		 || satisfies_constraint_eU (op)
-		 || satisfies_constraint_eV (op)")
-
+		 || satisfies_constraint_eI (op)")
     (match_operand 0 "gpc_reg_operand")))
 
 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 1af38698bf3..976a42a74cd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,17 +139,6 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
     case ENB_MMA:
       error ("%qs requires the %qs option", name, "-mmma");
       break;
-    case ENB_FUTURE:
-      error ("%qs requires the %qs option", name, "-mcpu=future");
-      break;
-    case ENB_FUTURE_64:
-      error ("%qs requires the %qs option and either the %qs or %qs option",
-	     name, "-mcpu=future", "-m64", "-mpowerpc64");
-      break;
-    case ENB_DM:
-      error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
-	     "-mdense-math");
-      break;
     default:
     case ENB_ALWAYS:
       gcc_unreachable ();
@@ -205,12 +194,6 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
       return TARGET_HTM;
     case ENB_MMA:
       return TARGET_MMA;
-    case ENB_FUTURE:
-      return TARGET_FUTURE;
-    case ENB_FUTURE_64:
-      return TARGET_FUTURE && TARGET_POWERPC64;
-    case ENB_DM:
-      return TARGET_DENSE_MATH;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 437ab0e09e9..3bc7fed6956 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -139,8 +139,6 @@
 ;   endian   Needs special handling for endianness
 ;   ibmld    Restrict usage to the case when TFmode is IBM-128
 ;   ibm128   Restrict usage to the case where __ibm128 is supported or if ibmld
-;   future   Restrict usage to future instructions
-;   dm       Restrict usage to dense math
 ;
 ; Each attribute corresponds to extra processing required when
 ; the built-in is expanded.  All such special processing should
@@ -4133,11 +4131,3 @@
 
   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
     STXVP nothing {mma,pair}
-
-[future]
-  const signed int __builtin_saturate_subtract32 (signed int, signed int);
-  SAT_SUBSI sat_subsi3 {}
-
-[future-64]
-  const signed long __builtin_saturate_subtract64 (signed long,  signed long);
-  SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index f0461e5817a..acd44058876 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -451,8 +451,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11");
   if ((flags & OPTION_MASK_FUTURE) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE");
-  if ((flags & OPTION_MASK_FUTURE2) != 0)
-    rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE2");
   if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
   if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index fee97c96197..4ddba142e44 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -93,9 +93,6 @@
 				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_FUTURE)
 
-#define ISA_FUTURE2_MASKS_SERVER (ISA_FUTURE_MASKS_SERVER		\
-				  | OPTION_MASK_FUTURE2)
-
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS	(OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
@@ -136,7 +133,6 @@
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
 				 | OPTION_MASK_FPRND			\
 				 | OPTION_MASK_FUTURE			\
-				 | OPTION_MASK_FUTURE2			\
 				 | OPTION_MASK_POWER10			\
 				 | OPTION_MASK_POWER11			\
 				 | OPTION_MASK_P10_FUSION		\
@@ -273,4 +269,3 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
 RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
 RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER)
-RS6000_CPU ("future2", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE2_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc b/gcc/config/rs6000/rs6000-gen-builtins.cc
index acd65d4bd0a..e32d1e2d134 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -233,9 +233,6 @@ enum bif_stanza
  BSTZ_P10,
  BSTZ_P10_64,
  BSTZ_MMA,
- BSTZ_FUTURE,
- BSTZ_FUTURE_64,
- BSTZ_DM,
  NUMBIFSTANZAS
 };
 
@@ -269,10 +266,7 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] =
     { "htm",		BSTZ_HTM	},
     { "power10",	BSTZ_P10	},
     { "power10-64",	BSTZ_P10_64	},
-    { "mma",		BSTZ_MMA	},
-    { "future",		BSTZ_FUTURE	},
-    { "future-64",	BSTZ_FUTURE_64	},
-    { "dm",		BSTZ_DM		},
+    { "mma",		BSTZ_MMA	}
   };
 
 static const char *enable_string[NUMBIFSTANZAS] =
@@ -297,10 +291,7 @@ static const char *enable_string[NUMBIFSTANZAS] =
     "ENB_HTM",
     "ENB_P10",
     "ENB_P10_64",
-    "ENB_MMA",
-    "ENB_FUTURE",
-    "ENB_FUTURE_64",
-    "ENB_DM",
+    "ENB_MMA"
   };
 
 /* Function modifiers provide special handling for const, pure, and fpmath
@@ -404,8 +395,6 @@ struct attrinfo
   bool isendian;
   bool isibmld;
   bool isibm128;
-  bool isfuture;
-  bool isdm;
 };
 
 /* Fields associated with a function prototype (bif or overload).  */
@@ -1488,8 +1477,7 @@ parse_bif_attrs (attrinfo *attrptr)
 	"ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, "
 	"htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, "
 	"mmaint = %d, no32bit = %d, 32bit = %d, cpu = %d, ldstmask = %d, "
-	"lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d,",
-	"future = %d, dm = %d.\n",
+	"lxvrse = %d, lxvrze = %d, endian = %d, ibmdld = %d, ibm128 = %d.\n",
 	attrptr->isinit, attrptr->isset, attrptr->isextract,
 	attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec,
 	attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr,
@@ -1497,7 +1485,7 @@ parse_bif_attrs (attrinfo *attrptr)
 	attrptr->ismmaint, attrptr->isno32bit, attrptr->is32bit,
 	attrptr->iscpu, attrptr->isldstmask, attrptr->islxvrse,
 	attrptr->islxvrze, attrptr->isendian, attrptr->isibmld,
-	attrptr->isibm128, attrptr->isfuture, attrptr->isdm);
+	attrptr->isibm128);
 #endif
 
   return PC_OK;
@@ -2269,10 +2257,7 @@ write_decls (void)
   fprintf (header_file, "  ENB_HTM,\n");
   fprintf (header_file, "  ENB_P10,\n");
   fprintf (header_file, "  ENB_P10_64,\n");
-  fprintf (header_file, "  ENB_MMA,\n");
-  fprintf (header_file, "  ENB_FUTURE,\n");
-  fprintf (header_file, "  ENB_FUTURE_64,\n");
-  fprintf (header_file, "  ENB_DM\n");
+  fprintf (header_file, "  ENB_MMA\n");
   fprintf (header_file, "};\n\n");
 
   fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n");
@@ -2316,8 +2301,6 @@ write_decls (void)
   fprintf (header_file, "#define bif_endian_bit\t\t(0x00200000)\n");
   fprintf (header_file, "#define bif_ibmld_bit\t\t(0x00400000)\n");
   fprintf (header_file, "#define bif_ibm128_bit\t\t(0x00800000)\n");
-  fprintf (header_file, "#define bif_future_bit\t\t(0x01000000)\n");
-  fprintf (header_file, "#define bif_dm_bit\t\t(0x02000000)\n");
   fprintf (header_file, "\n");
   fprintf (header_file,
 	   "#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n");
@@ -2367,10 +2350,6 @@ write_decls (void)
 	   "#define bif_is_ibmld(x)\t((x).bifattrs & bif_ibmld_bit)\n");
   fprintf (header_file,
 	   "#define bif_is_ibm128(x)\t((x).bifattrs & bif_ibm128_bit)\n");
-  fprintf (header_file,
-	   "#define bif_is_future(x)\t((x).bifattrs & bif_future_bit)\n");
-  fprintf (header_file,
-	   "#define bif_is_dm(x)\t((x).bifattrs & bif_dm_bit)\n");
   fprintf (header_file, "\n");
 
   fprintf (header_file,
@@ -2569,10 +2548,6 @@ write_bif_static_init (void)
 	fprintf (init_file, " | bif_ibmld_bit");
       if (bifp->attrs.isibm128)
 	fprintf (init_file, " | bif_ibm128_bit");
-      if (bifp->attrs.isfuture)
-	fprintf (init_file, " | bif_future_bit");
-      if (bifp->attrs.isdm)
-	fprintf (init_file, " | bif_dm_bit");
       fprintf (init_file, ",\n");
       fprintf (init_file, "      /* restr_opnd */\t{%d, %d, %d},\n",
 	       bifp->proto.restr_opnd[0], bifp->proto.restr_opnd[1],
diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc
index c6737e66cbe..e74ccf41937 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2787,7 +2787,6 @@ expand_block_move (rtx operands[], bool might_overlap)
 
       if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
 	  && TARGET_BLOCK_OPS_VECTOR_PAIR
-	  && TARGET_POWERPC64
 	  && bytes >= 32
 	  && (align >= 256 || !STRICT_ALIGNMENT))
 	{
diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt
index 291e295331e..f009c4e5718 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -203,6 +203,3 @@ Enum(rs6000_cpu_opt_value) String(power11) Value(57)
 EnumValue
 Enum(rs6000_cpu_opt_value) String(future) Value(58)
 
-EnumValue
-Enum(rs6000_cpu_opt_value) String(future2) Value(59)
-
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 93f1a99c80f..573602d0c11 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4307,7 +4307,6 @@ rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_PCREL;
     }
 
-
   /* Print the options after updating the defaults.  */
   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
     rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
@@ -6118,14 +6117,6 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
   else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
     return 1;
 
-  /* PADDIS support.  */
-  else if (TARGET_PADDIS && TARGET_POWERPC64
-	   && !IN_RANGE (value >> 32, -1, 0)
-	   && (SIGNED_INTEGER_32BIT_P (value >> 32)))
-    return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
-	    ? 1
-	    : 2);
-
   else if (TARGET_POWERPC64)
     {
       int num_insns = 0;
@@ -6146,14 +6137,6 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
 {
   int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
   int total = 0;
-  if (nregs == 1
-      && TARGET_PADDIS && TARGET_POWERPC64
-      && !IN_RANGE (value >> 32, -1, 0)
-      && SIGNED_INTEGER_32BIT_P (value >> 32))
-    return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
-	    ? 1
-	    : 2);
-
   while (nregs-- > 0)
     {
       HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
@@ -14228,14 +14211,6 @@ print_operand (FILE *file, rtx x, int code)
 	fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
       return;
 
-    case 'B':
-      /* Upper 32-bits of a constant.  */
-      if (!CONST_INT_P (x))
-	output_operand_lossage ("Not a constant.");
-
-      fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32);
-      return;
-
     case 'D':
       /* Like 'J' but get to the GT bit only.  */
       if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 37afa67f184..67ef3d3a7d0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -106,7 +106,6 @@
    you make changes here, make them also there.  */
 #define ASM_CPU_SPEC \
 "%{mcpu=native: %(asm_cpu_native); \
-  mcpu=future2: -mfuture; \
   mcpu=future: -mfuture; \
   mcpu=power11: -mpower11; \
   mcpu=power10: -mpower10; \
@@ -574,9 +573,6 @@ extern int rs6000_vector_align[];
    below.  */
 #define RS6000_FN_TARGET_INFO_HTM 1
 
-/* Whether we have PADDIS support.  */
-#define TARGET_PADDIS			TARGET_FUTURE2
-
 /* Whether the various reciprocal divide/square root estimate instructions
    exist, and whether we should automatically generate code for the instruction
    by default.  */
@@ -2499,7 +2495,6 @@ typedef struct GTY(()) machine_function
 	    (HOST_WIDE_INT_1 << ((N)-1)) - 1)
 
 #define SIGNED_INTEGER_16BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 16)
-#define SIGNED_INTEGER_32BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 32)
 #define SIGNED_INTEGER_34BIT_P(VALUE)	SIGNED_INTEGER_NBIT_P (VALUE, 34)
 
 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f96a228d1ba..2ccd83c9092 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -357,7 +357,7 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,paddis"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
   (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -405,11 +405,6 @@
      (and (eq_attr "isa" "p10")
 	  (match_test "TARGET_POWER10"))
      (const_int 1)
-
-     (and (eq_attr "isa" "paddis")
-	  (match_test "TARGET_PADDIS"))
-     (const_int 1)
-
     ] (const_int 0)))
 
 ;; If this instruction is microcoded on the CELL processor
@@ -1815,42 +1810,17 @@
 })
 
 (define_insn "*add<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r,r,b")
-	(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b,b,b")
-		  (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))]
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+	(plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")
+		  (match_operand:GPR 2 "add_operand" "r,I,L,eI")))]
   ""
   "@
    add %0,%1,%2
    addi %0,%1,%2
    addis %0,%1,%v2
-   addi %0,%1,%2
-   paddis %0,%1,%B2
-   #"
+   addi %0,%1,%2"
   [(set_attr "type" "add")
-   (set_attr "isa" "*,*,*,p10,paddis,paddis")
-   (set_attr "length" "*,*,*,*,12,24")
-   (set_attr "prefixed" "*,*,*,*,yes,yes")
-   (set_attr "maybe_prefixed" "*,*,*,*,no,no")])
-
-(define_split
-  [(set (match_operand:DI 0 "gpc_reg_operand")
-	(plus:DI (match_operand:DI 1 "gpc_reg_operand")
-		 (match_operand:DI 2 "paddis_paddi_operand")))]
-  "TARGET_PADDIS && TARGET_POWERPC64"
-  [(set (match_dup 3)
-	(plus:DI (match_dup 1)
-		 (match_dup 4)))
-   (set (match_dup 0)
-	(plus:DI (match_dup 3)
-		 (match_dup 5)))]
-{
-  HOST_WIDE_INT value = INTVAL (operands[2]);
-  operands[3] = (can_create_pseudo_p ()
-		 ? gen_reg_rtx (DImode)
-		 : operands[0]);
-  operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
-  operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
+   (set_attr "isa" "*,*,*,p10")])
 
 (define_insn "*addsi3_high"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -9865,7 +9835,7 @@
   DONE;
 })
 
-;;	   GPR store   GPR load    GPR move    GPR paddis   GPR paddis+paddi
+;;	   GPR store   GPR load    GPR move
 ;;	   GPR li      GPR lis     GPR pli     GPR #
 ;;	   FPR store   FPR load    FPR move
 ;;	   AVX store   AVX store   AVX load    AVX load    VSX move
@@ -9875,7 +9845,7 @@
 ;;	   VSX->GPR    GPR->VSX
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-	  "=YZ,        r,          r,          r,          b,
+	  "=YZ,        r,          r,
 	   r,          r,          r,          r,
 	   m,          ^d,         ^d,
 	   wY,         Z,          $v,         $v,         ^wa,
@@ -9884,7 +9854,7 @@
 	   r,          *h,         *h,
 	   ?r,         ?wa")
 	(match_operand:DI 1 "input_operand"
-	  "r,          YZ,         r,          eU,         eV,
+	  "r,          YZ,         r,
 	   I,          L,          eI,         nF,
 	   ^d,         m,          ^d,
 	   ^v,         $v,         wY,         Z,          ^wa,
@@ -9899,8 +9869,6 @@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
    mr %0,%1
-   paddis %0,0,%B1
-   #
    li %0,%1
    lis %0,%v1
    li %0,%1
@@ -9926,7 +9894,7 @@
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
   [(set_attr "type"
-	  "store,      load,       *,          *,          *,
+	  "store,      load,       *,
 	   *,          *,          *,          *,
 	   fpstore,    fpload,     fpsimple,
 	   fpstore,    fpstore,    fpload,     fpload,     veclogical,
@@ -9936,7 +9904,7 @@
 	   mfvsr,      mtvsr")
    (set_attr "size" "64")
    (set_attr "length"
-	  "*,          *,          *,          12,         24,
+	  "*,          *,          *,
 	   *,          *,          *,          20,
 	   *,          *,          *,
 	   *,          *,          *,          *,          *,
@@ -9945,32 +9913,14 @@
 	   *,          *,          *,
 	   *,          *")
    (set_attr "isa"
-	  "*,          *,          *,          paddis,     paddis,
+	  "*,          *,          *,
 	   *,          *,          p10,        *,
 	   *,          *,          *,
 	   p9v,        p7v,        p9v,        p7v,        *,
 	   p9v,        p9v,        p7v,        *,          *,
 	   p7v,        p7v,
 	   *,          *,          *,
-	   p8v,        p8v")
-   (set_attr "prefixed"
-	  "*,          *,          *,          yes,        yes,
-	   *,          *,          *,          *,
-	   *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,
-	   *,          *,          *,
-	   *,          *")
-   (set_attr "maybe_prefixed"
-	  "*,          *,          *,          no,         no,
-	   *,          *,          *,          *,
-	   *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,          *,          *,          *,
-	   *,          *,
-	   *,          *,          *,
-	   *,          *")])
+	   p8v,        p8v")])
 
 ; Some DImode loads are best done as a load of -1 followed by a mask
 ; instruction.
@@ -9988,26 +9938,6 @@
 		(match_dup 1)))]
   "")
 
-;; Split a constant that can be generated by a paddis and paddi into 2
-;; instructions.
-(define_split
-  [(set (match_operand:DI 0 "int_reg_operand")
-	(match_operand:DI 1 "paddis_paddi_operand"))]
-  "TARGET_PADDIS && TARGET_POWERPC64"
-  [(set (match_dup 2)
-	(match_dup 3))
-   (set (match_dup 0)
-	(plus:DI (match_dup 2)
-		 (match_dup 4)))]
-{
-  HOST_WIDE_INT value = INTVAL (operands[1]);
-  operands[2] = (can_create_pseudo_p ()
-		 ? gen_reg_rtx (DImode)
-		 : operands[0]);
-  operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
-  operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
-
 ;; Split a load of a large constant into the appropriate five-instruction
 ;; sequence.  Handle anything in a constant number of insns.
 ;; When non-easy constants can go in the TOC, this should use
@@ -15892,66 +15822,6 @@
 }
   [(set_attr "type" "load")])
 \f
-;; Signed saturation.
-
-;; The subfus instruction is defined as: SUBFUS RT,L,RA,RB.  The extended
-;; mnemonic that we use (subdus and subwus) has the arguments RA and RB
-;; reversed (so it becomes a subtract instead of subtract from).
-
-(define_insn "sat_sub<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-		      (match_operand:GPR 2 "gpc_reg_operand" "r")))]
-  "TARGET_FUTURE"
-  "sub<wd>us %0,%1,%2"
-  [(set_attr "type" "add")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-				  (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:GPR 0 "=r,r"))]
-  "TARGET_FUTURE"
-  "@
-   sub<wd>us. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "add")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-(define_insn_and_split "*sat_sub<mode>3_dot2"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-	(compare:CC (ss_minus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
-				  (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))]
-  "TARGET_FUTURE"
-  "@
-   sub<wd>us. %0,%1,%2
-   #"
-  "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
-  [(set (match_dup 0)
-	(ss_minus:GPR (match_dup 1)
-		      (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  ""
-  [(set_attr "type" "add")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-\f
 
 (include "sync.md")
 (include "vector.md")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 97120a0b64b..621ebd65a88 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -587,10 +587,6 @@ Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpowe
 mfuture
 Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>)
 
-;; Possible future bits beyound -mcpu=future
-mfuture2
-Target Undocumented Mask(FUTURE2) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture2>)
-
 mprefixed
 Target Mask(PREFIXED) Var(rs6000_isa_flags)
 Generate (do not generate) prefixed memory instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9520191e613..f135fa079bd 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5629,32 +5629,20 @@
   DONE;
 })
 
-;; Load VSX Vector with Length.  If we have lxvrl, we don't have to do an
-;; explicit shift left into a pseudo.
+;; Load VSX Vector with Length
 (define_expand "lxvl"
-  [(use (match_operand:V16QI 0 "vsx_register_operand"))
-   (use (match_operand:DI 1 "gpc_reg_operand"))
-   (use (match_operand:DI 2 "gpc_reg_operand"))]
+  [(set (match_dup 3)
+        (ashift:DI (match_operand:DI 2 "register_operand")
+                   (const_int 56)))
+   (set (match_operand:V16QI 0 "vsx_register_operand")
+	(unspec:V16QI
+	 [(match_operand:DI 1 "gpc_reg_operand")
+          (mem:V16QI (match_dup 1))
+	  (match_dup 3)]
+	 UNSPEC_LXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
-  rtx len;
-
-  if (TARGET_FUTURE)
-    len = shift_len;
-  else
-    {
-      len = gen_reg_rtx (DImode);
-      emit_insn (gen_rtx_SET (len, shift_len));
-    }
-
-  rtx dest = operands[0];
-  rtx addr = operands[1];
-  rtx mem = gen_rtx_MEM (V16QImode, addr);
-  rtvec rv = gen_rtvec (3, addr, mem, len);
-  rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
-  emit_insn (gen_rtx_SET (dest, lxvl));
-  DONE;
+  operands[3] = gen_reg_rtx (DImode);
 })
 
 (define_insn "*lxvl"
@@ -5678,34 +5666,6 @@
   "lxvll %x0,%1,%2"
   [(set_attr "type" "vecload")])
 
-;; For lxvrl and lxvrll, use the combiner to eliminate the shift.  The
-;; define_expand for lxvl will already incorporate the shift in generating the
-;; insn.  The lxvll buitl-in function required the user to have already done
-;; the shift.  Defining lxvrll this way, will optimize cases where the user has
-;; done the shift immediately before the built-in.
-(define_insn "*lxvrl"
-  [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-	(unspec:V16QI
-	 [(match_operand:DI 1 "gpc_reg_operand" "b")
-	  (mem:V16QI (match_dup 1))
-	  (ashift:DI (match_operand:DI 2 "register_operand" "r")
-		     (const_int 56))]
-	 UNSPEC_LXVL))]
-  "TARGET_FUTURE && TARGET_64BIT"
-  "lxvrl %x0,%1,%2"
-  [(set_attr "type" "vecload")])
-
-(define_insn "*lxvrll"
-  [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
-	(unspec:V16QI [(match_operand:DI 1 "gpc_reg_operand" "b")
-                       (mem:V16QI (match_dup 1))
-		       (ashift:DI (match_operand:DI 2 "register_operand" "r")
-				  (const_int 56))]
-		      UNSPEC_LXVLL))]
-  "TARGET_FUTURE"
-  "lxvrll %x0,%1,%2"
-  [(set_attr "type" "vecload")])
-
 ;; Expand for builtin xl_len_r
 (define_expand "xl_len_r"
   [(match_operand:V16QI 0 "vsx_register_operand")
@@ -5737,29 +5697,18 @@
 
 ;; Store VSX Vector with Length
 (define_expand "stxvl"
-  [(use (match_operand:V16QI 0 "vsx_register_operand"))
-   (use (match_operand:DI 1 "gpc_reg_operand"))
-   (use (match_operand:DI 2 "gpc_reg_operand"))]
+  [(set (match_dup 3)
+	(ashift:DI (match_operand:DI 2 "register_operand")
+		   (const_int 56)))
+   (set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand"))
+	(unspec:V16QI
+	 [(match_operand:V16QI 0 "vsx_register_operand")
+	  (mem:V16QI (match_dup 1))
+	  (match_dup 3)]
+	 UNSPEC_STXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
 {
-  rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
-  rtx len;
-
-  if (TARGET_FUTURE)
-    len = shift_len;
-  else
-    {
-      len = gen_reg_rtx (DImode);
-      emit_insn (gen_rtx_SET (len, shift_len));
-    }
-
-  rtx src = operands[0];
-  rtx addr = operands[1];
-  rtx mem = gen_rtx_MEM (V16QImode, addr);
-  rtvec rv = gen_rtvec (3, src, mem, len);
-  rtx stxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_STXVL);
-  emit_insn (gen_rtx_SET (mem, stxvl));
-  DONE;
+  operands[3] = gen_reg_rtx (DImode);
 })
 
 ;; Define optab for vector access with length vectorization exploitation.
@@ -5803,35 +5752,6 @@
   "stxvl %x0,%1,%2"
   [(set_attr "type" "vecstore")])
 
-;; For stxvrl and stxvrll, use the combiner to eliminate the shift.  The
-;; define_expand for stxvl will already incorporate the shift in generating the
-;; insn.  The stxvll buitl-in function required the user to have already done
-;; the shift.  Defining stxvrll this way, will optimize cases where the user
-;; has done the shift immediately before the built-in.
-
-(define_insn "*stxvrl"
-  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
-	(unspec:V16QI
-	 [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-	  (mem:V16QI (match_dup 1))
-	  (ashift:DI (match_operand:DI 2 "register_operand" "r")
-		     (const_int 56))]
-	 UNSPEC_STXVL))]
-  "TARGET_FUTURE && TARGET_64BIT"
-  "stxvrl %x0,%1,%2"
-  [(set_attr "type" "vecstore")])
-
-(define_insn "*stxvrll"
-  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
-	(unspec:V16QI [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-		       (mem:V16QI (match_dup 1))
-		       (ashift:DI (match_operand:DI 2 "register_operand" "r")
-				  (const_int 56))]
-	              UNSPEC_STXVLL))]
-  "TARGET_FUTURE"
-  "stxvrll %x0,%1,%2"
-  [(set_attr "type" "vecstore")])
-
 ;; Expand for builtin xst_len_r
 (define_expand "xst_len_r"
   [(match_operand:V16QI 0 "vsx_register_operand" "=wa")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 713e7ee96c0..7b54a241a7b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -20963,7 +20963,6 @@ Reverse the bit order of a 64-bit unsigned integer.
 * Basic PowerPC Built-in Functions Available on ISA 2.07::
 * Basic PowerPC Built-in Functions Available on ISA 3.0::
 * Basic PowerPC Built-in Functions Available on ISA 3.1::
-* Basic Built-in Functions that may be available on future PowerPCs::
 @end menu
 
 This section describes PowerPC built-in functions that do not require
@@ -21615,29 +21614,6 @@ ISA 3.1 @code{stxvrbx}, @code{stxvrhx}, @code{stxvrwx}, and @code{stxvrdx}
 instructions.
 @enddefbuiltin
 
-@node Basic Built-in Functions that may be available on future PowerPCs
-@subsubsection Potential future PowerPC Built-in Functions
-
-The built-in functions described in this section may be available on
-future PowerPC processors.  At present, these built-ins exist to
-allowing testing of new instructions.  There is no guarantee that
-these instructions will actually be implemented.
-
-The following built-in functions are available on Linux 64-bit systems
-that use a potential future instruction set (@option{-mcpu=future}):
-
-@table @code
-@item int __builtin_saturate_subtract32 (int, int)
-Subtract the second operand from the first operand.  If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-
-@item long __builtin_saturate_subtract64 (long, long)
-Subtract the second operand from the first operand.  If the value
-would be less than 0, then the result is 0 instead of the negative
-value of the subtraction.
-@end table
-
 @node PowerPC AltiVec/VSX Built-in Functions
 @subsection PowerPC AltiVec/VSX Built-in Functions
 
diff --git a/gcc/testsuite/gcc.target/powerpc/lxvrl.c b/gcc/testsuite/gcc.target/powerpc/lxvrl.c
deleted file mode 100644
index 71854c50c91..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/lxvrl.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the lxvrl and stxvrl instructions are generated for
-   -mcpu=future on memory copy operations.  */
-
-#ifndef VSIZE
-#define VSIZE 2
-#endif
-
-#ifndef LSIZE
-#define LSIZE 5
-#endif
-
-struct foo {
-  vector unsigned char vc[VSIZE];
-  unsigned char leftover[LSIZE];
-};
-
-void memcpy_ptr (struct foo *p, struct foo *q)
-{
-  __builtin_memcpy ((void *) p,		/* lxvrl and stxvrl.  */
-		    (void *) q,
-		    (sizeof (vector unsigned char) * VSIZE) + LSIZE);
-}
-
-/* { dg-final { scan-assembler     {\mlxvrl\M}  } } */
-/* { dg-final { scan-assembler     {\mstxvrl\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvl\M}   } } */
-/* { dg-final { scan-assembler-not {\mstxvl\M}  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/paddis.c b/gcc/testsuite/gcc.target/powerpc/paddis.c
deleted file mode 100644
index 09c461b8e06..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/paddis.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future2 -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
-   Altivec registers is generated.  */
-
-#include <stddef.h>
-
-size_t
-prefix_addis_addi (size_t x)
-{
-  return x + 0x1234000056789ABCUL;
-}
-
-size_t
-prefix_addis (size_t x)
-{
-  return x + 0x123400000000000UL;
-}
-
-/* { dg-final { scan-assembler-times {\mpaddis\M} 2  } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M}  1  } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-1.c b/gcc/testsuite/gcc.target/powerpc/subfus-1.c
deleted file mode 100644
index 535e7f8483d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-1.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 32-bit
-   subtracts.  */
-
-int do_sat_int  (int  a, int  b)
-{
-  return __builtin_saturate_subtract32 (a, b);		/* subwus  */
-}
-
-int do_sat_int_dot  (int  a, int  b, int  *p)
-{
-  int  r = __builtin_saturate_subtract32 (a, b);	/* subwus.  */
-  if (r == 0)
-    *p = 0;
-
-  return r;
-}
-
-void do_sat_int_dot2  (int  a, int  b, int  *p, int *q)
-{
-  if (__builtin_saturate_subtract32 (a, b))		/* subwus.  */
-    *p = 0;
-
-  *q = a + b;
-  return;
-}
-
-/* { dg-final { scan-assembler     {\msubwus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/subfus-2.c b/gcc/testsuite/gcc.target/powerpc/subfus-2.c
deleted file mode 100644
index b68e66dd2b0..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/subfus-2.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_future_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the saturating subtract built-in generates subwus for 64-bit
-   subtracts.  */
-
-long do_sat_long  (long  a, long  b)
-{
-  return __builtin_saturate_subtract64 (a, b);		/* subwus  */
-}
-
-long do_sat_long_dot  (long  a, long  b, long  *p)
-{
-  long  r = __builtin_saturate_subtract64 (a, b);	/* subwus.  */
-  if (r == 0)
-    *p = 0;
-
-  return r;
-}
-
-void do_sat_long_dot2  (long  a, long  b, long  *p, long *q)
-{
-  if (__builtin_saturate_subtract64 (a, b))		/* subwus.  */
-    *p = 0;
-
-  *q = a + b;
-  return;
-}
-
-/* { dg-final { scan-assembler     {\msubdus\M} } } */
-/* { dg-final { scan-assembler-not {\msubf\M}   } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/xvrlw.c b/gcc/testsuite/gcc.target/powerpc/xvrlw.c
deleted file mode 100644
index f0a28a8a430..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/xvrlw.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
-   Altivec registers is generated.  */
-
-#include <altivec.h>
-
-typedef vector unsigned int  v4si_t;
-
-v4si_t
-rotl_v4si_scalar (v4si_t x, unsigned long n)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return (x << n) | (x >> (32 - n));
-}
-
-v4si_t
-rotr_v4si_scalar (v4si_t x, unsigned long n)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return (x >> n) | (x << (32 - n));
-}
-
-v4si_t
-rotl_v4si_vector (v4si_t x, v4si_t y)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return vec_rl (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mxvrl\M} 3  } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 9cd1fbe6cda..14b3737eecf 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7121,31 +7121,6 @@ proc check_effective_target_power11_ok { } {
     }
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the saturating subtract instruction.
-proc check_effective_target_powerpc_future_ok { } {
-       return [check_no_compiler_messages powerpc_future_ok object {
-           #ifndef _ARCH_PWR_FUTURE
-           #error "-mcpu=future is not supported"
-           #else
-           int dummy;
-           #endif
-       } "-mcpu=future"]
-}
-
-# Return 1 if this is a PowerPC target supporting -mcpu=future2 which enables
-# potential instructins beyond -mcpu=future.  Note, the assembler may not
-# have support for these instructions.
-proc check_effective_target_powerpc_future2_ok { } {
-       return [check_no_compiler_messages powerpc_future2_ok assembly {
-           #ifndef _ARCH_PWR_FUTURE2
-           #error "-mcpu=future2 is not supported"
-           #else
-           int dummy;
-           #endif
-       } "-mcpu=future2"]
-}
-
 # Return 1 if this is a PowerPC target supporting -mcpu=future which enables
 # the dense math operations.
 proc check_effective_target_powerpc_dense_math_ok { } {

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22  4:21 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22  4:21 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:90b5e76409a32556b7672139d6a2d031d0d5937e

commit 90b5e76409a32556b7672139d6a2d031d0d5937e
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 22 00:21:34 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/constraints.md  |  3 ---
 gcc/config/rs6000/mma.md          | 54 ++++++++++++++++++++-------------------
 gcc/config/rs6000/predicates.md   | 15 -----------
 gcc/config/rs6000/rs6000-c.cc     |  9 ++-----
 gcc/config/rs6000/rs6000-cpus.def |  2 --
 gcc/config/rs6000/rs6000.cc       |  7 +----
 gcc/config/rs6000/rs6000.h        |  1 -
 gcc/doc/md.texi                   |  5 ----
 8 files changed, 31 insertions(+), 65 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 277a30a8245..369a7b75042 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,9 +107,6 @@
        (match_test "TARGET_P8_VECTOR")
        (match_operand 0 "s5bit_cint_operand")))
 
-(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
-  "Accumulator register.")
-
 (define_constraint "wE"
   "@internal Vector constant that can be loaded with the XXSPLTIB instruction."
   (match_test "xxspltib_constant_nosplit (op, mode)"))
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 49cf5f8fe43..04e2d0066df 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -452,7 +452,8 @@
 	   (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa")
 	   (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")]
 	  UNSPECV_MMA_ASSEMBLE))]
-  "TARGET_MMA"
+  "TARGET_MMA
+   && fpr_reg_operand (operands[0], XOmode)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -485,7 +486,8 @@
        (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
 		      (match_operand 2 "const_0_to_3_operand")]
 		      UNSPEC_MMA_EXTRACT))]
-  "TARGET_MMA"
+  "TARGET_MMA
+   && fpr_reg_operand (operands[1], XOmode)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -502,8 +504,8 @@
 ;; the accumulator.  We enforce this by marking the output as early clobber.
 
 (define_insn "mma_<acc>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
 		    MMA_ACC))]
   "TARGET_MMA"
   "<acc> %A0"
@@ -513,7 +515,7 @@
 ;; UNSPEC_VOLATILE.
 
 (define_insn "mma_xxsetaccz"
-  [(set (match_operand:XO 0 "accumulator_operand" "=wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
 	(unspec_volatile:XO [(const_int 0)]
 			    UNSPECV_MMA_XXSETACCZ))]
   "TARGET_MMA"
@@ -521,7 +523,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<vv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
 		    MMA_VV))]
@@ -530,8 +532,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<avv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
 		    MMA_AVV))]
@@ -540,7 +542,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<pv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
 		    MMA_PV))]
@@ -549,8 +551,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<apv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
 		    MMA_APV))]
@@ -559,7 +561,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i8>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -572,8 +574,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i8>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -586,7 +588,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -599,8 +601,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -613,7 +615,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -625,8 +627,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -638,7 +640,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<pvi4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -650,8 +652,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<apvi4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -663,7 +665,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -676,8 +678,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2ef4256c72b..d23ce9a77a3 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -186,21 +186,6 @@
   return VLOGICAL_REGNO_P (REGNO (op));
 })
 
-;; Return 1 if op is an accumulator.  On power10 systems, the accumulators
-;; overlap with the FPRs.
-(define_predicate "accumulator_operand"
-  (match_operand 0 "register_operand")
-{
-  if (!REG_P (op))
-    return 0;
-
-  if (!HARD_REGISTER_P (op))
-    return 1;
-
-  int r = REGNO (op);
-  return FP_REGNO_P (r) && (r & 3) == 0;
-})
-
 ;; Return 1 if op is the carry register.
 (define_predicate "ca_operand"
   (match_operand 0 "register_operand")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index acd44058876..d15bb85743c 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -599,14 +599,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
   if (rs6000_cpu == PROCESSOR_CELL)
     rs6000_define_or_undefine_macro (define_p, "__PPU__");
 
-  /* Tell the user if we support the MMA instructions.  Also tell them if MMA
-     uses the dense math registers.  */
+  /* Tell the user if we support the MMA instructions.  */
   if ((flags & OPTION_MASK_MMA) != 0)
-    {
-      rs6000_define_or_undefine_macro (define_p, "__MMA__");
-      if ((flags & OPTION_MASK_FUTURE) != 0)
-	rs6000_define_or_undefine_macro (define_p, "__DENSE_MATH__");
-    }
+    rs6000_define_or_undefine_macro (define_p, "__MMA__");
   /* Whether pc-relative code is being generated.  */
   if ((flags & OPTION_MASK_PCREL) != 0)
     rs6000_define_or_undefine_macro (define_p, "__PCREL__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 4ddba142e44..47365534af8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
 				  | OPTION_MASK_POWER11)
 
 #define ISA_FUTURE_MASKS_SERVER	(ISA_POWER11_MASKS_SERVER		\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_FUTURE)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -122,7 +121,6 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 #define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_CMPB			\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DFP			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8b5f1da6cbb..2921e72aea8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2322,7 +2322,6 @@ rs6000_debug_reg_global (void)
 	   "wr reg_class = %s\n"
 	   "wx reg_class = %s\n"
 	   "wA reg_class = %s\n"
-	   "wD reg_class = %s\n"
 	   "\n",
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2330,8 +2329,7 @@ rs6000_debug_reg_global (void)
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
+	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
 
   nl = "\n";
   for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -2988,9 +2986,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   if (TARGET_DIRECT_MOVE_128)
     rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
 
-  if (TARGET_MMA)
-    rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;
-
   /* Set up the reload helper and direct move functions.  */
   if (TARGET_VSX || TARGET_ALTIVEC)
     {
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index fc3bd006c47..79ce1a8cbf1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1201,7 +1201,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wr,		/* GPR register if 64-bit  */
   RS6000_CONSTRAINT_wx,		/* FPR register for STFIWX */
   RS6000_CONSTRAINT_wA,		/* BASE_REGS if 64-bit.  */
-  RS6000_CONSTRAINT_wD,		/* Accumulator regs if MMA/Dense Math.  */
   RS6000_CONSTRAINT_MAX
 };
 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ac68a8e1cb7..5730bda80dc 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3440,11 +3440,6 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.
 @item wA
 Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
 
-@item wD
-Accumulator register if @option{-mma} is used; otherwise,
-@code{NO_REGS}.  For @option{-mcpu=power10} the accumulator registers
-overlap with VSX vector registers 0..31.
-
 @item wB
 Signed 5-bit constant integer that can be loaded into an Altivec register.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22  4:16 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22  4:16 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:8ed4af0366a9b0d8670b96dfba25b85d3ba9b65c

commit 8ed4af0366a9b0d8670b96dfba25b85d3ba9b65c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 22 00:16:08 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/constraints.md  |  3 ---
 gcc/config/rs6000/mma.md          | 54 ++++++++++++++++++++-------------------
 gcc/config/rs6000/predicates.md   | 15 -----------
 gcc/config/rs6000/rs6000-c.cc     |  9 ++-----
 gcc/config/rs6000/rs6000-cpus.def |  2 --
 gcc/config/rs6000/rs6000.cc       |  7 +----
 gcc/config/rs6000/rs6000.h        |  1 -
 gcc/doc/md.texi                   |  5 ----
 8 files changed, 31 insertions(+), 65 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 277a30a8245..369a7b75042 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,9 +107,6 @@
        (match_test "TARGET_P8_VECTOR")
        (match_operand 0 "s5bit_cint_operand")))
 
-(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
-  "Accumulator register.")
-
 (define_constraint "wE"
   "@internal Vector constant that can be loaded with the XXSPLTIB instruction."
   (match_test "xxspltib_constant_nosplit (op, mode)"))
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 49cf5f8fe43..04e2d0066df 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -452,7 +452,8 @@
 	   (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa")
 	   (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")]
 	  UNSPECV_MMA_ASSEMBLE))]
-  "TARGET_MMA"
+  "TARGET_MMA
+   && fpr_reg_operand (operands[0], XOmode)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -485,7 +486,8 @@
        (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
 		      (match_operand 2 "const_0_to_3_operand")]
 		      UNSPEC_MMA_EXTRACT))]
-  "TARGET_MMA"
+  "TARGET_MMA
+   && fpr_reg_operand (operands[1], XOmode)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -502,8 +504,8 @@
 ;; the accumulator.  We enforce this by marking the output as early clobber.
 
 (define_insn "mma_<acc>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
 		    MMA_ACC))]
   "TARGET_MMA"
   "<acc> %A0"
@@ -513,7 +515,7 @@
 ;; UNSPEC_VOLATILE.
 
 (define_insn "mma_xxsetaccz"
-  [(set (match_operand:XO 0 "accumulator_operand" "=wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
 	(unspec_volatile:XO [(const_int 0)]
 			    UNSPECV_MMA_XXSETACCZ))]
   "TARGET_MMA"
@@ -521,7 +523,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<vv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
 		    MMA_VV))]
@@ -530,8 +532,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<avv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
 		    MMA_AVV))]
@@ -540,7 +542,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<pv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
 		    MMA_PV))]
@@ -549,8 +551,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<apv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
 		    MMA_APV))]
@@ -559,7 +561,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i8>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -572,8 +574,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i8>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -586,7 +588,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -599,8 +601,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -613,7 +615,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -625,8 +627,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -638,7 +640,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<pvi4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -650,8 +652,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<apvi4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -663,7 +665,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -676,8 +678,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2ef4256c72b..d23ce9a77a3 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -186,21 +186,6 @@
   return VLOGICAL_REGNO_P (REGNO (op));
 })
 
-;; Return 1 if op is an accumulator.  On power10 systems, the accumulators
-;; overlap with the FPRs.
-(define_predicate "accumulator_operand"
-  (match_operand 0 "register_operand")
-{
-  if (!REG_P (op))
-    return 0;
-
-  if (!HARD_REGISTER_P (op))
-    return 1;
-
-  int r = REGNO (op);
-  return FP_REGNO_P (r) && (r & 3) == 0;
-})
-
 ;; Return 1 if op is the carry register.
 (define_predicate "ca_operand"
   (match_operand 0 "register_operand")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index acd44058876..d15bb85743c 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -599,14 +599,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
   if (rs6000_cpu == PROCESSOR_CELL)
     rs6000_define_or_undefine_macro (define_p, "__PPU__");
 
-  /* Tell the user if we support the MMA instructions.  Also tell them if MMA
-     uses the dense math registers.  */
+  /* Tell the user if we support the MMA instructions.  */
   if ((flags & OPTION_MASK_MMA) != 0)
-    {
-      rs6000_define_or_undefine_macro (define_p, "__MMA__");
-      if ((flags & OPTION_MASK_FUTURE) != 0)
-	rs6000_define_or_undefine_macro (define_p, "__DENSE_MATH__");
-    }
+    rs6000_define_or_undefine_macro (define_p, "__MMA__");
   /* Whether pc-relative code is being generated.  */
   if ((flags & OPTION_MASK_PCREL) != 0)
     rs6000_define_or_undefine_macro (define_p, "__PCREL__");
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 4ddba142e44..47365534af8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
 				  | OPTION_MASK_POWER11)
 
 #define ISA_FUTURE_MASKS_SERVER	(ISA_POWER11_MASKS_SERVER		\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_FUTURE)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -122,7 +121,6 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 #define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_CMPB			\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DFP			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 8b5f1da6cbb..2921e72aea8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2322,7 +2322,6 @@ rs6000_debug_reg_global (void)
 	   "wr reg_class = %s\n"
 	   "wx reg_class = %s\n"
 	   "wA reg_class = %s\n"
-	   "wD reg_class = %s\n"
 	   "\n",
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2330,8 +2329,7 @@ rs6000_debug_reg_global (void)
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
+	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
 
   nl = "\n";
   for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -2988,9 +2986,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   if (TARGET_DIRECT_MOVE_128)
     rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
 
-  if (TARGET_MMA)
-    rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;
-
   /* Set up the reload helper and direct move functions.  */
   if (TARGET_VSX || TARGET_ALTIVEC)
     {
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index fc3bd006c47..79ce1a8cbf1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1201,7 +1201,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wr,		/* GPR register if 64-bit  */
   RS6000_CONSTRAINT_wx,		/* FPR register for STFIWX */
   RS6000_CONSTRAINT_wA,		/* BASE_REGS if 64-bit.  */
-  RS6000_CONSTRAINT_wD,		/* Accumulator regs if MMA/Dense Math.  */
   RS6000_CONSTRAINT_MAX
 };
 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ac68a8e1cb7..5730bda80dc 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3440,11 +3440,6 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.
 @item wA
 Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
 
-@item wD
-Accumulator register if @option{-mma} is used; otherwise,
-@code{NO_REGS}.  For @option{-mcpu=power10} the accumulator registers
-overlap with VSX vector registers 0..31.
-
 @item wB
 Signed 5-bit constant integer that can be loaded into an Altivec register.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22  3:59 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22  3:59 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:889e9e1165b5f84cf84820ca9b1926548941aded

commit 889e9e1165b5f84cf84820ca9b1926548941aded
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 21 23:59:52 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/altivec.md                      |  14 -
 gcc/config/rs6000/constraints.md                  |   3 -
 gcc/config/rs6000/mma.md                          | 410 +++++-----------------
 gcc/config/rs6000/predicates.md                   |  32 --
 gcc/config/rs6000/rs6000-builtin.cc               |  22 +-
 gcc/config/rs6000/rs6000-call.cc                  |  10 +-
 gcc/config/rs6000/rs6000-cpus.def                 |   2 -
 gcc/config/rs6000/rs6000-modes.def                |   4 -
 gcc/config/rs6000/rs6000.cc                       | 318 ++++-------------
 gcc/config/rs6000/rs6000.h                        |  50 +--
 gcc/config/rs6000/rs6000.md                       |   2 -
 gcc/doc/md.texi                                   |   5 -
 gcc/testsuite/gcc.target/powerpc/dm-1024bit.c     |  63 ----
 gcc/testsuite/gcc.target/powerpc/dm-double-test.c | 194 ----------
 gcc/testsuite/lib/target-supports.exp             |  23 --
 15 files changed, 166 insertions(+), 986 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index afe3d72316c..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*future_xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_FUTURE"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 277a30a8245..369a7b75042 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -107,9 +107,6 @@
        (match_test "TARGET_P8_VECTOR")
        (match_operand 0 "s5bit_cint_operand")))
 
-(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
-  "Accumulator register.")
-
 (define_constraint "wE"
   "@internal Vector constant that can be loaded with the XXSPLTIB instruction."
   (match_test "xxspltib_constant_nosplit (op, mode)"))
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 4f9c59046ea..04e2d0066df 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -91,11 +91,6 @@
    UNSPEC_MMA_XVI8GER4SPP
    UNSPEC_MMA_XXMFACC
    UNSPEC_MMA_XXMTACC
-   UNSPEC_DM_INSERT512_UPPER
-   UNSPEC_DM_INSERT512_LOWER
-   UNSPEC_DM_EXTRACT512
-   UNSPEC_DMR_RELOAD_FROM_MEMORY
-   UNSPEC_DMR_RELOAD_TO_MEMORY
   ])
 
 (define_c_enum "unspecv"
@@ -229,47 +224,44 @@
 				 (UNSPEC_MMA_XVF64GERNP		"xvf64gernp")
 				 (UNSPEC_MMA_XVF64GERNN		"xvf64gernn")])
 
-;; The "pm" prefix is not in these expansions, so that we can generate
-;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems
-;; without dense math registers.
-(define_int_attr vvi4i4i8	[(UNSPEC_MMA_PMXVI4GER8		"xvi4ger8")])
+(define_int_attr vvi4i4i8	[(UNSPEC_MMA_PMXVI4GER8		"pmxvi4ger8")])
 
-(define_int_attr avvi4i4i8	[(UNSPEC_MMA_PMXVI4GER8PP	"xvi4ger8pp")])
+(define_int_attr avvi4i4i8	[(UNSPEC_MMA_PMXVI4GER8PP	"pmxvi4ger8pp")])
 
-(define_int_attr vvi4i4i2	[(UNSPEC_MMA_PMXVI16GER2	"xvi16ger2")
-				 (UNSPEC_MMA_PMXVI16GER2S	"xvi16ger2s")
-				 (UNSPEC_MMA_PMXVF16GER2	"xvf16ger2")
-				 (UNSPEC_MMA_PMXVBF16GER2	"xvbf16ger2")])
+(define_int_attr vvi4i4i2	[(UNSPEC_MMA_PMXVI16GER2	"pmxvi16ger2")
+				 (UNSPEC_MMA_PMXVI16GER2S	"pmxvi16ger2s")
+				 (UNSPEC_MMA_PMXVF16GER2	"pmxvf16ger2")
+				 (UNSPEC_MMA_PMXVBF16GER2	"pmxvbf16ger2")])
 
-(define_int_attr avvi4i4i2	[(UNSPEC_MMA_PMXVI16GER2PP	"xvi16ger2pp")
-				 (UNSPEC_MMA_PMXVI16GER2SPP	"xvi16ger2spp")
-				 (UNSPEC_MMA_PMXVF16GER2PP	"xvf16ger2pp")
-				 (UNSPEC_MMA_PMXVF16GER2PN	"xvf16ger2pn")
-				 (UNSPEC_MMA_PMXVF16GER2NP	"xvf16ger2np")
-				 (UNSPEC_MMA_PMXVF16GER2NN	"xvf16ger2nn")
-				 (UNSPEC_MMA_PMXVBF16GER2PP	"xvbf16ger2pp")
-				 (UNSPEC_MMA_PMXVBF16GER2PN	"xvbf16ger2pn")
-				 (UNSPEC_MMA_PMXVBF16GER2NP	"xvbf16ger2np")
-				 (UNSPEC_MMA_PMXVBF16GER2NN	"xvbf16ger2nn")])
+(define_int_attr avvi4i4i2	[(UNSPEC_MMA_PMXVI16GER2PP	"pmxvi16ger2pp")
+				 (UNSPEC_MMA_PMXVI16GER2SPP	"pmxvi16ger2spp")
+				 (UNSPEC_MMA_PMXVF16GER2PP	"pmxvf16ger2pp")
+				 (UNSPEC_MMA_PMXVF16GER2PN	"pmxvf16ger2pn")
+				 (UNSPEC_MMA_PMXVF16GER2NP	"pmxvf16ger2np")
+				 (UNSPEC_MMA_PMXVF16GER2NN	"pmxvf16ger2nn")
+				 (UNSPEC_MMA_PMXVBF16GER2PP	"pmxvbf16ger2pp")
+				 (UNSPEC_MMA_PMXVBF16GER2PN	"pmxvbf16ger2pn")
+				 (UNSPEC_MMA_PMXVBF16GER2NP	"pmxvbf16ger2np")
+				 (UNSPEC_MMA_PMXVBF16GER2NN	"pmxvbf16ger2nn")])
 
-(define_int_attr vvi4i4		[(UNSPEC_MMA_PMXVF32GER		"xvf32ger")])
+(define_int_attr vvi4i4		[(UNSPEC_MMA_PMXVF32GER		"pmxvf32ger")])
 
-(define_int_attr avvi4i4	[(UNSPEC_MMA_PMXVF32GERPP	"xvf32gerpp")
-				 (UNSPEC_MMA_PMXVF32GERPN	"xvf32gerpn")
-				 (UNSPEC_MMA_PMXVF32GERNP	"xvf32gernp")
-				 (UNSPEC_MMA_PMXVF32GERNN	"xvf32gernn")])
+(define_int_attr avvi4i4	[(UNSPEC_MMA_PMXVF32GERPP	"pmxvf32gerpp")
+				 (UNSPEC_MMA_PMXVF32GERPN	"pmxvf32gerpn")
+				 (UNSPEC_MMA_PMXVF32GERNP	"pmxvf32gernp")
+				 (UNSPEC_MMA_PMXVF32GERNN	"pmxvf32gernn")])
 
-(define_int_attr pvi4i2		[(UNSPEC_MMA_PMXVF64GER		"xvf64ger")])
+(define_int_attr pvi4i2		[(UNSPEC_MMA_PMXVF64GER		"pmxvf64ger")])
 
-(define_int_attr apvi4i2	[(UNSPEC_MMA_PMXVF64GERPP	"xvf64gerpp")
-				 (UNSPEC_MMA_PMXVF64GERPN	"xvf64gerpn")
-				 (UNSPEC_MMA_PMXVF64GERNP	"xvf64gernp")
-				 (UNSPEC_MMA_PMXVF64GERNN	"xvf64gernn")])
+(define_int_attr apvi4i2	[(UNSPEC_MMA_PMXVF64GERPP	"pmxvf64gerpp")
+				 (UNSPEC_MMA_PMXVF64GERPN	"pmxvf64gerpn")
+				 (UNSPEC_MMA_PMXVF64GERNP	"pmxvf64gernp")
+				 (UNSPEC_MMA_PMXVF64GERNN	"pmxvf64gernn")])
 
-(define_int_attr vvi4i4i4	[(UNSPEC_MMA_PMXVI8GER4		"xvi8ger4")])
+(define_int_attr vvi4i4i4	[(UNSPEC_MMA_PMXVI8GER4		"pmxvi8ger4")])
 
-(define_int_attr avvi4i4i4	[(UNSPEC_MMA_PMXVI8GER4PP	"xvi8ger4pp")
-				 (UNSPEC_MMA_PMXVI8GER4SPP	"xvi8ger4spp")])
+(define_int_attr avvi4i4i4	[(UNSPEC_MMA_PMXVI8GER4PP	"pmxvi8ger4pp")
+				 (UNSPEC_MMA_PMXVI8GER4SPP	"pmxvi8ger4spp")])
 
 
 ;; Vector pair support.  OOmode can only live in VSRs.
@@ -322,9 +314,7 @@
    (set_attr "length" "*,*,8")])
 
 \f
-;; Vector quad support.  Under the original MMA, XOmode can only live in VSX
-;; registers 0..31.  With dense math, XOmode can live in either VSX registers
-;; (0..63) or DMR registers.
+;; Vector quad support.  XOmode can only live in FPRs.
 (define_expand "movxo"
   [(set (match_operand:XO 0 "nonimmediate_operand")
 	(match_operand:XO 1 "input_operand"))]
@@ -349,10 +339,10 @@
     gcc_assert (false);
 })
 
-(define_insn_and_split "*movxo_nodm"
+(define_insn_and_split "*movxo"
   [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
 	(match_operand:XO 1 "input_operand" "ZwO,d,d"))]
-  "TARGET_MMA_NO_DENSE_MATH
+  "TARGET_MMA
    && (gpc_reg_operand (operands[0], XOmode)
        || gpc_reg_operand (operands[1], XOmode))"
   "@
@@ -369,31 +359,6 @@
    (set_attr "length" "*,*,16")
    (set_attr "max_prefixed_insns" "2,2,*")])
 
-(define_insn_and_split "*movxo_dm"
-  [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,ZwO,wa,wD,wD,wa")
-	(match_operand:XO 1 "input_operand"        "ZwO,wa, wa,wa,wD,wD"))]
-  "TARGET_MMA_DENSE_MATH
-   && (gpc_reg_operand (operands[0], XOmode)
-       || gpc_reg_operand (operands[1], XOmode))"
-  "@
-   #
-   #
-   #
-   dmxxinstdmr512 %0,%1,%Y1,0
-   dmmr %0,%1
-   dmxxextfdmr512 %0,%Y0,%1,0"
-  "&& reload_completed
-   && !dmr_operand (operands[0], XOmode)
-   && !dmr_operand (operands[1], XOmode)"
-  [(const_int 0)]
-{
-  rs6000_split_multireg_move (operands[0], operands[1]);
-  DONE;
-}
-  [(set_attr "type" "vecload,vecstore,veclogical,mma,mma,mma")
-   (set_attr "length" "*,*,16,*,*,*")
-   (set_attr "max_prefixed_insns" "2,2,*,*,*,*")])
-
 (define_expand "vsx_assemble_pair"
   [(match_operand:OO 0 "vsx_register_operand")
    (match_operand:V16QI 1 "mma_assemble_input_operand")
@@ -487,7 +452,8 @@
 	   (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa")
 	   (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")]
 	  UNSPECV_MMA_ASSEMBLE))]
-  "TARGET_MMA"
+  "TARGET_MMA
+   && fpr_reg_operand (operands[0], XOmode)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -520,7 +486,8 @@
        (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
 		      (match_operand 2 "const_0_to_3_operand")]
 		      UNSPEC_MMA_EXTRACT))]
-  "TARGET_MMA"
+  "TARGET_MMA
+   && fpr_reg_operand (operands[1], XOmode)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -532,17 +499,15 @@
   DONE;
 })
 
-;; MMA instructions that do not use their accumulators as an input, still must
-;; not allow their vector operands to overlap the registers used by the
-;; accumulator.  We enforce this by marking the output as early clobber.  The
-;; prime and de-prime instructions are not needed on systems with dense math
-;; registers.
+;; MMA instructions that do not use their accumulators as an input, still
+;; must not allow their vector operands to overlap the registers used by
+;; the accumulator.  We enforce this by marking the output as early clobber.
 
 (define_insn "mma_<acc>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
 	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
 		    MMA_ACC))]
-  "TARGET_MMA_NO_DENSE_MATH"
+  "TARGET_MMA"
   "<acc> %A0"
   [(set_attr "type" "mma")])
 
@@ -550,63 +515,53 @@
 ;; UNSPEC_VOLATILE.
 
 (define_insn "mma_xxsetaccz"
-  [(set (match_operand:XO 0 "accumulator_operand" "=wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
 	(unspec_volatile:XO [(const_int 0)]
 			    UNSPECV_MMA_XXSETACCZ))]
   "TARGET_MMA"
-{
-  return TARGET_DENSE_MATH ? "dmsetdmrz %A0" : "xxsetaccz %A0";
-}
+  "xxsetaccz %A0"
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<vv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
 		    MMA_VV))]
   "TARGET_MMA"
-{
-  return TARGET_DENSE_MATH ? "dm<vv> %A0,%x1,%x2" : "<vv> %A0,%x1,%x2";
-}
+  "<vv> %A0,%x1,%x2"
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<avv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
 		    MMA_AVV))]
   "TARGET_MMA"
-{
-  return TARGET_DENSE_MATH ? "dm<avv> %A0,%x2,%x3" : "<avv> %A0,%x2,%x3";
-}
+  "<avv> %A0,%x2,%x3"
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<pv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
 		    MMA_PV))]
   "TARGET_MMA"
-{
-  return TARGET_DENSE_MATH ? "dm<pv> %A0,%x1,%x2" : "<pv> %A0,%x1,%x2";
-}
+  "<pv> %A0,%x1,%x2"
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<apv>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
 		    MMA_APV))]
   "TARGET_MMA"
-{
-  return TARGET_DENSE_MATH ? "dm<apv> %A0,%x2,%x3" : "<apv> %A0,%x2,%x3";
-}
+  "<apv> %A0,%x2,%x3"
   [(set_attr "type" "mma")])
 
-(define_insn "mma_pm<vvi4i4i8>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+(define_insn "mma_<vvi4i4i8>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -614,17 +569,13 @@
 		    (match_operand:SI 5 "u8bit_cint_operand" "n,n")]
 		    MMA_VVI4I4I8))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
-          : "pm<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5");
-}
+  "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<avvi4i4i8>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+(define_insn "mma_<avvi4i4i8>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -632,16 +583,12 @@
 		    (match_operand:SI 6 "u8bit_cint_operand" "n,n")]
 		    MMA_AVVI4I4I8))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
-          : "pm<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6");
-}
+  "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<vvi4i4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+(define_insn "mma_<vvi4i4i2>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -649,17 +596,13 @@
 		    (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
 		    MMA_VVI4I4I2))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
-          : "pm<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5");
-}
+  "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<avvi4i4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+(define_insn "mma_<avvi4i4i2>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -667,82 +610,62 @@
 		    (match_operand:SI 6 "const_0_to_3_operand" "n,n")]
 		    MMA_AVVI4I4I2))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
-          : "pm<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6");
-}
+  "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<vvi4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+(define_insn "mma_<vvi4i4>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")]
 		    MMA_VVI4I4))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<vvi4i4> %A0,%x1,%x2,%3,%4"
-          : "pm<vvi4i4> %A0,%x1,%x2,%3,%4");
-}
+  "<vvi4i4> %A0,%x1,%x2,%3,%4"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<avvi4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+(define_insn "mma_<avvi4i4>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
 		    (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
 		    MMA_AVVI4I4))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<avvi4i4> %A0,%x2,%x3,%4,%5"
-          : "pm<avvi4i4> %A0,%x2,%x3,%4,%5");
-}
+  "<avvi4i4> %A0,%x2,%x3,%4,%5"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<pvi4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+(define_insn "mma_<pvi4i2>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
 		    (match_operand:SI 4 "const_0_to_3_operand" "n,n")]
 		    MMA_PVI4I2))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<pvi4i2> %A0,%x1,%x2,%3,%4"
-          : "pm<pvi4i2> %A0,%x1,%x2,%3,%4");
-}
+  "<pvi4i2> %A0,%x1,%x2,%3,%4"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<apvi4i2>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+(define_insn "mma_<apvi4i2>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
 		    (match_operand:SI 5 "const_0_to_3_operand" "n,n")]
 		    MMA_APVI4I2))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<apvi4i2> %A0,%x2,%x3,%4,%5"
-          : "pm<apvi4i2> %A0,%x2,%x3,%4,%5");
-}
+  "<apvi4i2> %A0,%x2,%x3,%4,%5"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<vvi4i4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+(define_insn "mma_<vvi4i4i4>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
 	(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -750,17 +673,13 @@
 		    (match_operand:SI 5 "const_0_to_15_operand" "n,n")]
 		    MMA_VVI4I4I4))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
-          : "pm<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5");
-}
+  "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
 
-(define_insn "mma_pm<avvi4i4i4>"
-  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
-	(unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
+(define_insn "mma_<avvi4i4i4>"
+  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+	(unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
 		    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
 		    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
 		    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -768,159 +687,6 @@
 		    (match_operand:SI 6 "const_0_to_15_operand" "n,n")]
 		    MMA_AVVI4I4I4))]
   "TARGET_MMA"
-{
-  return (TARGET_DENSE_MATH
-          ? "pmdm<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
-          : "pm<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6");
-}
+  "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
   [(set_attr "type" "mma")
    (set_attr "prefixed" "yes")])
-\f
-;; TDOmode (__dmr keyword for 1,024 bit registers).
-(define_expand "movtdo"
-  [(set (match_operand:TDO 0 "nonimmediate_operand")
-	(match_operand:TDO 1 "input_operand"))]
-  "TARGET_MMA_DENSE_MATH"
-{
-  rs6000_emit_move (operands[0], operands[1], TDOmode);
-  DONE;
-})
-
-(define_insn_and_split "*movtdo"
-  [(set (match_operand:TDO 0 "nonimmediate_operand" "=wa,m,wa,wD,wD,wa")
-	(match_operand:TDO 1 "input_operand" "m,wa,wa,wa,wD,wD"))]
-  "TARGET_MMA_DENSE_MATH
-   && (gpc_reg_operand (operands[0], TDOmode)
-       || gpc_reg_operand (operands[1], TDOmode))"
-  "@
-   #
-   #
-   #
-   #
-   dmmr %0,%1
-   #"
-  "&& reload_completed
-   && (!dmr_operand (operands[0], TDOmode) || !dmr_operand (operands[1], TDOmode))"
-  [(const_int 0)]
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  if (REG_P (op0) && REG_P (op1))
-    {
-      int regno0 = REGNO (op0);
-      int regno1 = REGNO (op1);
-
-      if (DMR_REGNO_P (regno0) && VSX_REGNO_P (regno1))
-	{
-	  rtx op1_upper = gen_rtx_REG (XOmode, regno1);
-	  rtx op1_lower = gen_rtx_REG (XOmode, regno1 + 4);
-	  emit_insn (gen_movtdo_insert512_upper (op0, op1_upper));
-	  emit_insn (gen_movtdo_insert512_lower (op0, op0, op1_lower));
-	  DONE;
-	}
-
-      else if (VSX_REGNO_P (regno0) && DMR_REGNO_P (regno1))
-	{
-	  rtx op0_upper = gen_rtx_REG (XOmode, regno0);
-	  rtx op0_lower = gen_rtx_REG (XOmode, regno0 + 4);
-	  emit_insn (gen_movtdo_extract512 (op0_upper, op1, const0_rtx));
-	  emit_insn (gen_movtdo_extract512 (op0_lower, op1, const1_rtx));
-	  DONE;
-	}
-
-     else
-	gcc_assert (VSX_REGNO_P (regno0) && VSX_REGNO_P (regno1));
-    }
-
-  rs6000_split_multireg_move (operands[0], operands[1]);
-  DONE;
-}
-  [(set_attr "type" "vecload,vecstore,vecmove,vecmove,vecmove,vecmove")
-   (set_attr "length" "*,*,32,8,*,8")
-   (set_attr "max_prefixed_insns" "4,4,*,*,*,*")])
-
-;; Move from VSX registers to DMR registers via two insert 512 bit
-;; instructions.
-(define_insn "movtdo_insert512_upper"
-  [(set (match_operand:TDO 0 "dmr_operand" "=wD")
-	(unspec:TDO [(match_operand:XO 1 "vsx_register_operand" "wa")]
-		    UNSPEC_DM_INSERT512_UPPER))]
-  "TARGET_MMA_DENSE_MATH"
-  "dmxxinstdmr512 %0,%1,%Y1,0"
-  [(set_attr "type" "mma")])
-
-(define_insn "movtdo_insert512_lower"
-  [(set (match_operand:TDO 0 "dmr_operand" "=wD")
-	(unspec:TDO [(match_operand:TDO 1 "dmr_operand" "0")
-		     (match_operand:XO 2 "vsx_register_operand" "wa")]
-		    UNSPEC_DM_INSERT512_LOWER))]
-  "TARGET_MMA_DENSE_MATH"
-  "dmxxinstdmr512 %0,%2,%Y2,1"
-  [(set_attr "type" "mma")])
-
-;; Move from DMR registers to VSX registers via two extract 512 bit
-;; instructions.
-(define_insn "movtdo_extract512"
-  [(set (match_operand:XO 0 "vsx_register_operand" "=wa")
-	(unspec:XO [(match_operand:TDO 1 "dmr_operand" "wD")
-		    (match_operand 2 "const_0_to_1_operand" "n")]
-		   UNSPEC_DM_EXTRACT512))]
-  "TARGET_MMA_DENSE_MATH"
-  "dmxxextfdmr512 %0,%Y0,%1,%2"
-  [(set_attr "type" "mma")])
-
-;; Reload DMR registers from memory
-(define_insn_and_split "reload_dmr_from_memory"
-  [(set (match_operand:TDO 0 "dmr_operand" "=wD")
-	(unspec:TDO [(match_operand:TDO 1 "memory_operand" "m")]
-		    UNSPEC_DMR_RELOAD_FROM_MEMORY))
-   (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))]
-  "TARGET_MMA_DENSE_MATH"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  rtx dest = operands[0];
-  rtx src = operands[1];
-  rtx tmp = operands[2];
-  rtx mem_upper = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 0 : 64);
-  rtx mem_lower = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 64 : 0);
-
-  emit_move_insn (tmp, mem_upper);
-  emit_insn (gen_movtdo_insert512_upper (dest, tmp));
-
-  emit_move_insn (tmp, mem_lower);
-  emit_insn (gen_movtdo_insert512_lower (dest, dest, tmp));
-  DONE;
-}
-  [(set_attr "length" "16")
-   (set_attr "max_prefixed_insns" "2")
-   (set_attr "type" "vecload")])
-
-;; Reload dense math registers to memory
-(define_insn_and_split "reload_dmr_to_memory"
-  [(set (match_operand:TDO 0 "memory_operand" "=m")
-	(unspec:TDO [(match_operand:TDO 1 "dmr_operand" "wD")]
-		    UNSPEC_DMR_RELOAD_TO_MEMORY))
-   (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))]
-  "TARGET_MMA_DENSE_MATH"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  rtx dest = operands[0];
-  rtx src = operands[1];
-  rtx tmp = operands[2];
-  rtx mem_upper = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 0 : 64);
-  rtx mem_lower = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 64 : 0);
-
-  emit_insn (gen_movtdo_extract512 (tmp, src, const0_rtx));
-  emit_move_insn (mem_upper, tmp);
-
-  emit_insn (gen_movtdo_extract512 (tmp, src, const1_rtx));
-  emit_move_insn (mem_lower, tmp);
-  DONE;
-}
-  [(set_attr "length" "16")
-   (set_attr "max_prefixed_insns" "2")])
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b325000690b..d23ce9a77a3 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -186,38 +186,6 @@
   return VLOGICAL_REGNO_P (REGNO (op));
 })
 
-;; Return 1 if op is a DMR register
-(define_predicate "dmr_operand"
-  (match_operand 0 "register_operand")
-{
-  if (!REG_P (op))
-    return 0;
-
-  if (!HARD_REGISTER_P (op))
-    return 1;
-
-  return DMR_REGNO_P (REGNO (op));
-})
-
-;; Return 1 if op is an accumulator.  On power10 systems, the accumulators
-;; overlap with the FPRs, while on systems with dense math, the accumulators
-;; are separate dense math registers and do not overlap with the FPR
-;; registers..
-(define_predicate "accumulator_operand"
-  (match_operand 0 "register_operand")
-{
-  if (!REG_P (op))
-    return 0;
-
-  if (!HARD_REGISTER_P (op))
-    return 1;
-
-  int r = REGNO (op);
-  return (TARGET_MMA_DENSE_MATH
-	  ? DMR_REGNO_P (r)
-	  : FP_REGNO_P (r) && (r & 3) == 0);
-})
-
 ;; Return 1 if op is the carry register.
 (define_predicate "ca_operand"
   (match_operand 0 "register_operand")
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 976a42a74cd..f3ba1eccdbd 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -495,8 +495,6 @@ const char *rs6000_type_string (tree type_node)
     return "__vector_pair";
   else if (type_node == vector_quad_type_node)
     return "__vector_quad";
-  else if (type_node == dmr_type_node)
-    return "__dmr";
 
   return "unknown";
 }
@@ -783,21 +781,6 @@ rs6000_init_builtins (void)
   t = build_qualified_type (vector_quad_type_node, TYPE_QUAL_CONST);
   ptr_vector_quad_type_node = build_pointer_type (t);
 
-  /* For TDOmode (1,024 bit dense math accumulators), don't use an alignment of
-     1,024, use 512.  TDOmode loads and stores are always broken up into 2
-     vector pair loads or stores.  In addition, we don't have support for
-     aligning the stack to 1,024 bits.  */
-  dmr_type_node = make_node (OPAQUE_TYPE);
-  SET_TYPE_MODE (dmr_type_node, TDOmode);
-  TYPE_SIZE (dmr_type_node) = bitsize_int (GET_MODE_BITSIZE (TDOmode));
-  TYPE_PRECISION (dmr_type_node) = GET_MODE_BITSIZE (TDOmode);
-  TYPE_SIZE_UNIT (dmr_type_node) = size_int (GET_MODE_SIZE (TDOmode));
-  SET_TYPE_ALIGN (dmr_type_node, 512);
-  TYPE_USER_ALIGN (dmr_type_node) = 0;
-  lang_hooks.types.register_builtin_type (dmr_type_node, "__dmr");
-  t = build_qualified_type (dmr_type_node, TYPE_QUAL_CONST);
-  ptr_dmr_type_node = build_pointer_type (t);
-
   tdecl = add_builtin_type ("__bool char", bool_char_type_node);
   TYPE_NAME (bool_char_type_node) = tdecl;
 
@@ -1139,9 +1122,8 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi,
 	}
 
       /* If we're disassembling an accumulator into a different type, we need
-	 to emit a xxmfacc instruction now, since we cannot do it later.  If we
-	 have dense math registers, we don't need to do this.  */
-      if (fncode == RS6000_BIF_DISASSEMBLE_ACC && !TARGET_DENSE_MATH)
+	 to emit a xxmfacc instruction now, since we cannot do it later.  */
+      if (fncode == RS6000_BIF_DISASSEMBLE_ACC)
 	{
 	  new_decl = rs6000_builtin_decls[RS6000_BIF_XXMFACC_INTERNAL];
 	  new_call = gimple_build_call (new_decl, 1, src);
diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc
index 5cda8375902..8c590903c86 100644
--- a/gcc/config/rs6000/rs6000-call.cc
+++ b/gcc/config/rs6000/rs6000-call.cc
@@ -437,15 +437,14 @@ rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
   if (cfun
       && !cfun->machine->mma_return_type_error
       && TREE_TYPE (cfun->decl) == fntype
-      && OPAQUE_MODE_P (TYPE_MODE (type)))
+      && (TYPE_MODE (type) == OOmode || TYPE_MODE (type) == XOmode))
     {
       /* Record we have now handled function CFUN, so the next time we
 	 are called, we do not re-report the same error.  */
       cfun->machine->mma_return_type_error = true;
       if (TYPE_CANONICAL (type) != NULL_TREE)
 	type = TYPE_CANONICAL (type);
-      error ("invalid use of %s type %qs as a function return value",
-	     (TYPE_MODE (type) == TDOmode) ? "dense math" : "MMA",
+      error ("invalid use of MMA type %qs as a function return value",
 	     IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));
     }
 
@@ -1633,12 +1632,11 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
   int n_elts;
 
   /* We do not allow MMA types being used as function arguments.  */
-  if (OPAQUE_MODE_P (mode))
+  if (mode == OOmode || mode == XOmode)
     {
       if (TYPE_CANONICAL (type) != NULL_TREE)
 	type = TYPE_CANONICAL (type);
-      error ("invalid use of %s operand of type %qs as a function parameter",
-	     (mode == TDOmode) ? "dense math" : "MMA",
+      error ("invalid use of MMA operand of type %qs as a function parameter",
 	     IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))));
       return NULL_RTX;
     }
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 4ddba142e44..47365534af8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,6 @@
 				  | OPTION_MASK_POWER11)
 
 #define ISA_FUTURE_MASKS_SERVER	(ISA_POWER11_MASKS_SERVER		\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_FUTURE)
 
 /* Flags that need to be turned off if -mno-vsx.  */
@@ -122,7 +121,6 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 #define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
-				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
 				 | OPTION_MASK_CMPB			\
 				 | OPTION_MASK_CRYPTO			\
 				 | OPTION_MASK_DFP			\
diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 43d839bf30c..094b246c834 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -86,7 +86,3 @@ PARTIAL_INT_MODE (TI, 128, PTI);
 /* Modes used by __vector_pair and __vector_quad.  */
 OPAQUE_MODE (OO, 32);
 OPAQUE_MODE (XO, 64);
-
-/* Mode used by __dmr.  */
-OPAQUE_MODE (TDO, 128);
-
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 573602d0c11..2921e72aea8 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -292,8 +292,7 @@ enum rs6000_reg_type {
   ALTIVEC_REG_TYPE,
   FPR_REG_TYPE,
   SPR_REG_TYPE,
-  CR_REG_TYPE,
-  DMR_REG_TYPE
+  CR_REG_TYPE
 };
 
 /* Map register class to register type.  */
@@ -307,23 +306,22 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
 
 
 /* Register classes we care about in secondary reload or go if legitimate
-   address.  We only need to worry about GPR, FPR, Altivec, and DMR registers
-   here, along an ANY field that is the OR of the 4 register classes.  */
+   address.  We only need to worry about GPR, FPR, and Altivec registers here,
+   along an ANY field that is the OR of the 3 register classes.  */
 
 enum rs6000_reload_reg_type {
   RELOAD_REG_GPR,			/* General purpose registers.  */
   RELOAD_REG_FPR,			/* Traditional floating point regs.  */
   RELOAD_REG_VMX,			/* Altivec (VMX) registers.  */
-  RELOAD_REG_DMR,			/* DMR registers.  */
-  RELOAD_REG_ANY,			/* OR of GPR/FPR/VMX/DMR masks.  */
+  RELOAD_REG_ANY,			/* OR of GPR, FPR, Altivec masks.  */
   N_RELOAD_REG
 };
 
-/* For setting up register classes, loop through the 4 register classes mapping
+/* For setting up register classes, loop through the 3 register classes mapping
    into real registers, and skip the ANY class, which is just an OR of the
    bits.  */
 #define FIRST_RELOAD_REG_CLASS	RELOAD_REG_GPR
-#define LAST_RELOAD_REG_CLASS	RELOAD_REG_DMR
+#define LAST_RELOAD_REG_CLASS	RELOAD_REG_VMX
 
 /* Map reload register type to a register in the register class.  */
 struct reload_reg_map_type {
@@ -335,7 +333,6 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
   { "Gpr",	FIRST_GPR_REGNO },	/* RELOAD_REG_GPR.  */
   { "Fpr",	FIRST_FPR_REGNO },	/* RELOAD_REG_FPR.  */
   { "VMX",	FIRST_ALTIVEC_REGNO },	/* RELOAD_REG_VMX.  */
-  { "DMR",	FIRST_DMR_REGNO },	/* RELOAD_REG_DMR.  */
   { "Any",	-1 },			/* RELOAD_REG_ANY.  */
 };
 
@@ -1229,8 +1226,6 @@ char rs6000_reg_names[][8] =
       "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
   /* vrsave vscr sfp */
       "vrsave", "vscr", "sfp",
-  /* DMRs */
-      "0", "1", "2", "3", "4", "5", "6", "7",
 };
 
 #ifdef TARGET_REGNAMES
@@ -1257,8 +1252,6 @@ static const char alt_reg_names[][8] =
   "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
   /* vrsave vscr sfp */
   "vrsave", "vscr", "sfp",
-  /* DMRs */
-  "%dmr0", "%dmr1", "%dmr2", "%dmr3", "%dmr4", "%dmr5", "%dmr6", "%dmr7",
 };
 #endif
 
@@ -1836,17 +1829,13 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
      128-bit floating point that can go in vector registers, which has VSX
      memory addressing.  */
   if (FP_REGNO_P (regno))
-    reg_size = (VECTOR_MEM_VSX_P (mode)
-		|| VECTOR_ALIGNMENT_P (mode)
+    reg_size = (VECTOR_MEM_VSX_P (mode) || VECTOR_ALIGNMENT_P (mode)
 		? UNITS_PER_VSX_WORD
 		: UNITS_PER_FP_WORD);
 
   else if (ALTIVEC_REGNO_P (regno))
     reg_size = UNITS_PER_ALTIVEC_WORD;
 
-  else if (DMR_REGNO_P (regno))
-    reg_size = UNITS_PER_DMR_WORD;
-
   else
     reg_size = UNITS_PER_WORD;
 
@@ -1868,35 +1857,9 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
   if (mode == OOmode)
     return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0);
 
-  /* On ISA 3.1 (power10), MMA accumulator modes need FPR registers divisible
-     by 4.
-
-     If dense math registers are enabled, we can allow all VSX registers plus
-     the DMR registers.  VSX registers are used to load and store the registers
-     as the accumulator registers do not have load and store instructions.
-     Because we just use the VSX registers for load/store operations, we just
-     need to make sure load vector pair and store vector pair instructions can
-     be used.  */
-  if (mode == XOmode || mode == TDOmode)
-    {
-      if (!TARGET_MMA)
-	return 0;
-
-      else if (!TARGET_DENSE_MATH)
-	return (mode == XOmode && FP_REGNO_P (regno) && (regno & 3) == 0);
-
-      else if (DMR_REGNO_P (regno))
-	return 1;
-
-      else
-	return (VSX_REGNO_P (regno)
-		&& VSX_REGNO_P (last_regno)
-		&& (regno & 1) == 0);
-    }
-
-  /* No other types other than XOmode or TDOmode can go in DMRs.  */
-  if (DMR_REGNO_P (regno))
-    return 0;
+  /* MMA accumulator modes need FPR registers divisible by 4.  */
+  if (mode == XOmode)
+    return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0);
 
   /* PTImode can only go in GPRs.  Quad word memory operations require even/odd
      register combinations, and use PTImode where we need to deal with quad
@@ -2002,11 +1965,9 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
    GPR registers, and TImode can go in any GPR as well as VSX registers (PR
    57744).
 
-   Similarly, don't allow OOmode (vector pair), XOmode (vector quad), or
-   TDOmode (dmr register) to pair with anything else.  Vector pairs are
-   restricted to even/odd VSX registers.  Without dense math, vector quads are
-   limited to FPR registers divisible by 4.  With dense math, vector quads are
-   limited to even VSX registers or DMR registers.
+   Similarly, don't allow OOmode (vector pair, restricted to even VSX
+   registers) or XOmode (vector quad, restricted to FPR registers divisible
+   by 4) to tie with other modes.
 
    Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
    128-bit floating point on VSX systems ties with other vectors.  */
@@ -2015,8 +1976,7 @@ static bool
 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
 {
   if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode
-      || mode1 == TDOmode || mode2 == PTImode || mode2 == OOmode
-      || mode2 == XOmode || mode2 == TDOmode)
+      || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode)
     return mode1 == mode2;
 
   if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
@@ -2307,7 +2267,6 @@ rs6000_debug_reg_global (void)
     V4DFmode,
     OOmode,
     XOmode,
-    TDOmode,
     CCmode,
     CCUNSmode,
     CCEQmode,
@@ -2343,7 +2302,6 @@ rs6000_debug_reg_global (void)
   rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
 			  LAST_ALTIVEC_REGNO,
 			  "vs");
-  rs6000_debug_reg_print (FIRST_DMR_REGNO, LAST_DMR_REGNO, "dmr");
   rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
   rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
   rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
@@ -2364,7 +2322,6 @@ rs6000_debug_reg_global (void)
 	   "wr reg_class = %s\n"
 	   "wx reg_class = %s\n"
 	   "wA reg_class = %s\n"
-	   "wD reg_class = %s\n"
 	   "\n",
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2372,8 +2329,7 @@ rs6000_debug_reg_global (void)
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
 	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
-	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
+	   reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
 
   nl = "\n";
   for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -2670,21 +2626,6 @@ rs6000_setup_reg_addr_masks (void)
 	  addr_mask = 0;
 	  reg = reload_reg_map[rc].reg;
 
-	  /* Special case DMR registers.  */
-	  if (rc == RELOAD_REG_DMR)
-	    {
-	      if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == TDOmode))
-		{
-		  addr_mask = RELOAD_REG_VALID;
-		  reg_addr[m].addr_mask[rc] = addr_mask;
-		  any_addr_mask |= addr_mask;
-		}
-	      else
-		reg_addr[m].addr_mask[rc] = 0;
-
-	      continue;
-	    }
-
 	  /* Can mode values go in the GPR/FPR/Altivec registers?  */
 	  if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
 	    {
@@ -2780,10 +2721,10 @@ rs6000_setup_reg_addr_masks (void)
 
 	  /* Vector pairs can do both indexed and offset loads if the
 	     instructions are enabled, otherwise they can only do offset loads
-	     since it will be broken into two vector moves.  Vector quads and
-	     dense math types can only do offset loads.  */
+	     since it will be broken into two vector moves.  Vector quads can
+	     only do offset loads.  */
 	  else if ((addr_mask != 0) && TARGET_MMA
-		   && (m2 == OOmode || m2 == XOmode || m2 == TDOmode))
+		   && (m2 == OOmode || m2 == XOmode))
 	    {
 	      addr_mask |= RELOAD_REG_OFFSET;
 	      if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
@@ -2835,9 +2776,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
     rs6000_regno_regclass[r] = CR_REGS;
 
-  for (r = FIRST_DMR_REGNO; r <= LAST_DMR_REGNO; ++r)
-    rs6000_regno_regclass[r] = DM_REGS;
-
   rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
   rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
   rs6000_regno_regclass[CA_REGNO] = NO_REGS;
@@ -2862,7 +2800,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
   reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
   reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
-  reg_class_to_reg_type[(int)DM_REGS] = DMR_REG_TYPE;
 
   if (TARGET_VSX)
     {
@@ -3011,14 +2948,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
       rs6000_vector_align[XOmode] = 512;
     }
 
-  /* Add support for 1,024 bit DMR registers.  */
-  if (TARGET_DENSE_MATH)
-    {
-      rs6000_vector_unit[TDOmode] = VECTOR_NONE;
-      rs6000_vector_mem[TDOmode] = VECTOR_VSX;
-      rs6000_vector_align[TDOmode] = 512;
-    }
-
   /* Register class constraints for the constraints that depend on compile
      switches. When the VSX code was added, different constraints were added
      based on the type (DFmode, V2DFmode, V4SFmode).  For the vector types, all
@@ -3057,12 +2986,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   if (TARGET_DIRECT_MOVE_128)
     rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
 
-  /* Support for the accumulator registers, either FPR registers (aka original
-     mma) or DMR registers (dense math).  */
-  if (TARGET_MMA)
-    rs6000_constraints[RS6000_CONSTRAINT_wD]
-      = TARGET_DENSE_MATH ? DM_REGS : FLOAT_REGS;
-
   /* Set up the reload helper and direct move functions.  */
   if (TARGET_VSX || TARGET_ALTIVEC)
     {
@@ -3231,12 +3154,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 	}
     }
 
-  if (TARGET_DENSE_MATH)
-    {
-      reg_addr[TDOmode].reload_load = CODE_FOR_reload_dmr_from_memory;
-      reg_addr[TDOmode].reload_store = CODE_FOR_reload_dmr_to_memory;
-    }
-
   /* Precalculate HARD_REGNO_NREGS.  */
   for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
     for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -8720,15 +8637,12 @@ reg_offset_addressing_ok_p (machine_mode mode)
 	return mode_supports_dq_form (mode);
       break;
 
-      /* The vector pair/quad types and the dense math types support offset
-	 addressing if the underlying vectors support offset addressing.  */
+      /* The vector pair/quad types support offset addressing if the
+	 underlying vectors support offset addressing.  */
     case E_OOmode:
     case E_XOmode:
       return TARGET_MMA;
 
-    case E_TDOmode:
-      return TARGET_DENSE_MATH;
-
     case E_SDmode:
       /* If we can do direct load/stores of SDmode, restrict it to reg+reg
 	 addressing for the LFIWZX and STFIWX instructions.  */
@@ -11279,12 +11193,6 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
 	       (mode == OOmode) ? "__vector_pair" : "__vector_quad");
       break;
 
-    case E_TDOmode:
-      if (CONST_INT_P (operands[1]))
-	error ("%qs is an opaque type, and you cannot set it to constants",
-	       "__dmr");
-      break;
-
     case E_SImode:
     case E_DImode:
       /* Use default pattern for address of ELF small data */
@@ -12413,11 +12321,6 @@ rs6000_secondary_reload_memory (rtx addr,
     addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
 		 & ~RELOAD_REG_AND_M16);
 
-  /* DMR registers use VSX registers for memory operations, and need to
-     generate some extra instructions.  */
-  else if (rclass == DM_REGS)
-    return 2;
-
   /* If the register allocator hasn't made up its mind yet on the register
      class to use, settle on defaults to use.  */
   else if (rclass == NO_REGS)
@@ -12746,13 +12649,6 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
 	       || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
     return true;
 
-  /* We can transfer between VSX registers and DMR registers without needing
-     extra registers.  */
-  if (TARGET_DENSE_MATH && (mode == XOmode || mode == TDOmode)
-      && ((to_type == DMR_REG_TYPE && from_type == VSX_REG_TYPE)
-	  || (to_type == VSX_REG_TYPE && from_type == DMR_REG_TYPE)))
-    return true;
-
   return false;
 }
 
@@ -13447,10 +13343,6 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
   machine_mode mode = GET_MODE (x);
   bool is_constant = CONSTANT_P (x);
 
-  /* DMR registers can't be loaded or stored.  */
-  if (rclass == DM_REGS)
-    return NO_REGS;
-
   /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
      reload class for it.  */
   if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
@@ -13547,10 +13439,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
 	return VSX_REGS;
 
       if (mode == XOmode)
-	return TARGET_MMA_DENSE_MATH ? VSX_REGS : FLOAT_REGS;
-
-      if (mode == TDOmode)
-	return VSX_REGS;
+	return FLOAT_REGS;
 
       if (GET_MODE_CLASS (mode) == MODE_INT)
 	return GENERAL_REGS;
@@ -13675,11 +13564,6 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
   else
     regno = -1;
 
-  /* DMR registers don't have loads or stores.  We have to go through the VSX
-     registers to load XOmode (vector quad).  */
-  if (TARGET_MMA_DENSE_MATH && rclass == DM_REGS)
-    return VSX_REGS;
-
   /* If we have VSX register moves, prefer moving scalar values between
      Altivec registers and GPR by going via an FPR (and then via memory)
      instead of reloading the secondary memory address for Altivec moves.  */
@@ -14193,19 +14077,8 @@ print_operand (FILE *file, rtx x, int code)
 	 output_operand.  */
 
     case 'A':
-      /* Write the MMA accumulator number associated with VSX register X.  On
-	 dense math systems, only allow DMR accumulators, not accumulators
-	 overlapping with the FPR registers.  */
-      if (!REG_P (x))
-	output_operand_lossage ("invalid %%A value");
-      else if (TARGET_MMA_DENSE_MATH)
-	{
-	  if (DMR_REGNO_P (REGNO (x)))
-	    fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
-	  else
-	    output_operand_lossage ("%%A operand is not a DMR");
-	}
-      else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
+      /* Write the MMA accumulator number associated with VSX register X.  */
+      if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
 	output_operand_lossage ("invalid %%A value");
       else
 	fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
@@ -20776,8 +20649,6 @@ rs6000_mangle_type (const_tree type)
     return "u13__vector_pair";
   if (type == vector_quad_type_node)
     return "u13__vector_quad";
-  if (type == dmr_type_node)
-    return "u5__dmr";
 
   /* For all other types, use the default mangling.  */
   return NULL;
@@ -22885,35 +22756,6 @@ rs6000_debug_address_cost (rtx x, machine_mode mode,
 }
 
 
-/* Subroutine to determine the move cost of dense math registers.  If we are
-   moving to/from VSX_REGISTER registers, the cost is either 1 move (for
-   512-bit accumulators) or 2 moves (for 1,024 dmr registers).  If we are
-   moving to anything else like GPR registers, make the cost very high.  */
-
-static int
-rs6000_dmr_register_move_cost (machine_mode mode, reg_class_t rclass)
-{
-  const int reg_move_base = 2;
-  HARD_REG_SET vsx_set = (reg_class_contents[rclass]
-			  & reg_class_contents[VSX_REGS]);
-
-  if (TARGET_MMA_DENSE_MATH && !hard_reg_set_empty_p (vsx_set))
-    {
-      /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction.  */
-      if (mode == XOmode)
-	return reg_move_base;
-
-      /* __dmr (i.e. TDOmode) is transferred in 2 instructions.  */
-      else if (mode == TDOmode)
-	return reg_move_base * 2;
-
-      else
-	return reg_move_base * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
-    }
-
-  return 1000 * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
-}
-
 /* A C expression returning the cost of moving data from a register of class
    CLASS1 to one of CLASS2.  */
 
@@ -22927,28 +22769,17 @@ rs6000_register_move_cost (machine_mode mode,
   if (TARGET_DEBUG_COST)
     dbg_cost_ctrl++;
 
-  HARD_REG_SET to_vsx, from_vsx;
-  to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
-  from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
-
-  /* Special case DMR registers, that can only move to/from VSX registers.  */
-  if (from == DM_REGS && to == DM_REGS)
-    ret = 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
-
-  else if (from == DM_REGS)
-    ret = rs6000_dmr_register_move_cost (mode, to);
-
-  else if (to == DM_REGS)
-    ret = rs6000_dmr_register_move_cost (mode, from);
-
   /* If we have VSX, we can easily move between FPR or Altivec registers,
      otherwise we can only easily move within classes.
      Do this first so we give best-case answers for union classes
      containing both gprs and vsx regs.  */
-  else if (!hard_reg_set_empty_p (to_vsx)
-	   && !hard_reg_set_empty_p (from_vsx)
-	   && (TARGET_VSX
-	       || hard_reg_set_intersect_p (to_vsx, from_vsx)))
+  HARD_REG_SET to_vsx, from_vsx;
+  to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
+  from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
+  if (!hard_reg_set_empty_p (to_vsx)
+      && !hard_reg_set_empty_p (from_vsx)
+      && (TARGET_VSX
+	  || hard_reg_set_intersect_p (to_vsx, from_vsx)))
     {
       int reg = FIRST_FPR_REGNO;
       if (TARGET_VSX
@@ -23045,9 +22876,6 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
     ret = 4 * hard_regno_nregs (32, mode);
   else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
     ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
-  else if (reg_classes_intersect_p (rclass, DM_REGS))
-    ret = (rs6000_dmr_register_move_cost (mode, VSX_REGS)
-	   + rs6000_memory_move_cost (mode, VSX_REGS, false));
   else
     ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
 
@@ -24256,8 +24084,6 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
       if (TARGET_HARD_FLOAT)
 	pressure_classes[n++] = FLOAT_REGS;
     }
-  if (TARGET_MMA_DENSE_MATH)
-    pressure_classes[n++] = DM_REGS;
   pressure_classes[n++] = CR_REGS;
   pressure_classes[n++] = SPECIAL_REGS;
 
@@ -24422,10 +24248,6 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format)
     return 67;
   if (regno == 64)
     return 64;
-  /* XXX: This is a guess.  The GCC register number for FIRST_DMR_REGNO is 111,
-     but the frame pointer regnum uses that.  */
-  if (DMR_REGNO_P (regno))
-    return regno - FIRST_DMR_REGNO + 112;
 
   gcc_unreachable ();
 }
@@ -27596,10 +27418,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
   mode = GET_MODE (dst);
   nregs = hard_regno_nregs (reg, mode);
 
-  /* If we have a vector quad register for MMA or DMR register for dense math,
-     and this is a load or store, see if we can use vector paired
-     load/stores.  */
-  if ((mode == XOmode || mode == TDOmode) && TARGET_MMA
+  /* If we have a vector quad register for MMA, and this is a load or store,
+     see if we can use vector paired load/stores.  */
+  if (mode == XOmode && TARGET_MMA
       && (MEM_P (dst) || MEM_P (src)))
     {
       reg_mode = OOmode;
@@ -27607,7 +27428,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
     }
   /* If we have a vector pair/quad mode, split it into two/four separate
      vectors.  */
-  else if (mode == OOmode || mode == XOmode || mode == TDOmode)
+  else if (mode == OOmode || mode == XOmode)
     reg_mode = V1TImode;
   else if (FP_REGNO_P (reg))
     reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
@@ -27653,13 +27474,13 @@ rs6000_split_multireg_move (rtx dst, rtx src)
       return;
     }
 
-  /* The __vector_pair, __vector_quad, and __dmr modes are multi-register
-     modes, so if we have to load or store the registers, we have to be careful
-     to properly swap them if we're in little endian mode below.  This means
-     the last register gets the first memory location.  We also need to be
-     careful of using the right register numbers if we are splitting XO to
-     OO.  */
-  if (mode == OOmode || mode == XOmode || mode == TDOmode)
+  /* The __vector_pair and __vector_quad modes are multi-register
+     modes, so if we have to load or store the registers, we have to be
+     careful to properly swap them if we're in little endian mode
+     below.  This means the last register gets the first memory
+     location.  We also need to be careful of using the right register
+     numbers if we are splitting XO to OO.  */
+  if (mode == OOmode || mode == XOmode)
     {
       nregs = hard_regno_nregs (reg, mode);
       int reg_mode_nregs = hard_regno_nregs (reg, reg_mode);
@@ -27668,9 +27489,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 	  unsigned offset = 0;
 	  unsigned size = GET_MODE_SIZE (reg_mode);
 
-	  /* If we are reading an accumulator register, we have to deprime it
-	     before we can access it unless we have dense math registers.  */
-	  if (TARGET_MMA_NO_DENSE_MATH
+	  /* If we are reading an accumulator register, we have to
+	     deprime it before we can access it.  */
+	  if (TARGET_MMA
 	      && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
 	    emit_insn (gen_mma_xxmfacc (src, src));
 
@@ -27702,9 +27523,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 	      emit_insn (gen_rtx_SET (dst2, src2));
 	    }
 
-	  /* If we are writing an accumulator register, we have to prime it
-	     after we've written it unless we have dense math registers.  */
-	  if (TARGET_MMA_NO_DENSE_MATH
+	  /* If we are writing an accumulator register, we have to
+	     prime it after we've written it.  */
+	  if (TARGET_MMA
 	      && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
 	    emit_insn (gen_mma_xxmtacc (dst, dst));
 
@@ -27718,9 +27539,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 		      || XINT (src, 1) == UNSPECV_MMA_ASSEMBLE);
 	  gcc_assert (REG_P (dst));
 	  if (GET_MODE (src) == XOmode)
-	    gcc_assert ((TARGET_MMA_DENSE_MATH
-			 ? VSX_REGNO_P (REGNO (dst))
-			 : FP_REGNO_P (REGNO (dst))));
+	    gcc_assert (FP_REGNO_P (REGNO (dst)));
 	  if (GET_MODE (src) == OOmode)
 	    gcc_assert (VSX_REGNO_P (REGNO (dst)));
 
@@ -27773,9 +27592,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 	      emit_insn (gen_rtx_SET (dst_i, op));
 	    }
 
-	  /* We are writing an accumulator register, so we have to prime it
-	     after we've written it unless we have dense math registers.  */
-	  if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH)
+	  /* We are writing an accumulator register, so we have to
+	     prime it after we've written it.  */
+	  if (GET_MODE (src) == XOmode)
 	    emit_insn (gen_mma_xxmtacc (dst, dst));
 
 	  return;
@@ -27786,9 +27605,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 
   if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
     {
-      /* If we are reading an accumulator register, we have to deprime it
-	 before we can access it unless we have dense math registers.  */
-      if (TARGET_MMA_NO_DENSE_MATH
+      /* If we are reading an accumulator register, we have to
+	 deprime it before we can access it.  */
+      if (TARGET_MMA
 	  && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
 	emit_insn (gen_mma_xxmfacc (src, src));
 
@@ -27796,7 +27615,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 	 overlap.  */
       int i;
       /* XO/OO are opaque so cannot use subregs. */
-      if (mode == OOmode || mode == XOmode || mode == TDOmode)
+      if (mode == OOmode || mode == XOmode )
 	{
 	  for (i = nregs - 1; i >= 0; i--)
 	    {
@@ -27814,9 +27633,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 							 i * reg_mode_size)));
 	}
 
-      /* If we are writing an accumulator register, we have to prime it after
-	 we've written it unless we have dense math registers.  */
-      if (TARGET_MMA_NO_DENSE_MATH
+      /* If we are writing an accumulator register, we have to
+	 prime it after we've written it.  */
+      if (TARGET_MMA
 	  && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
 	emit_insn (gen_mma_xxmtacc (dst, dst));
     }
@@ -27951,9 +27770,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 	    gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
 	}
 
-      /* If we are reading an accumulator register, we have to deprime it
-	 before we can access it unless we have dense math registers.  */
-      if (TARGET_MMA_NO_DENSE_MATH && REG_P (src)
+      /* If we are reading an accumulator register, we have to
+	 deprime it before we can access it.  */
+      if (TARGET_MMA && REG_P (src)
 	  && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))
 	emit_insn (gen_mma_xxmfacc (src, src));
 
@@ -27970,7 +27789,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 	    continue;
 
 	  /* XO/OO are opaque so cannot use subregs. */
-	  if (mode == OOmode || mode == XOmode || mode == TDOmode)
+	  if (mode == OOmode || mode == XOmode )
 	    {
 	      rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + j);
 	      rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + j);
@@ -27983,9 +27802,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 							 j * reg_mode_size)));
 	}
 
-      /* If we are writing an accumulator register, we have to prime it after
-	 we've written it unless we have dense math registers.  */
-      if (TARGET_MMA_NO_DENSE_MATH && REG_P (dst)
+      /* If we are writing an accumulator register, we have to
+	 prime it after we've written it.  */
+      if (TARGET_MMA && REG_P (dst)
 	  && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))
 	emit_insn (gen_mma_xxmtacc (dst, dst));
 
@@ -28952,8 +28771,7 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype)
 
   if (frommode != tomode)
     {
-      /* Do not allow conversions to/from XOmode, OOmode, and TDOmode
-	 types.  */
+      /* Do not allow conversions to/from XOmode and OOmode types.  */
       if (frommode == XOmode)
 	return N_("invalid conversion from type %<__vector_quad%>");
       if (tomode == XOmode)
@@ -28962,10 +28780,6 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype)
 	return N_("invalid conversion from type %<__vector_pair%>");
       if (tomode == OOmode)
 	return N_("invalid conversion to type %<__vector_pair%>");
-      if (frommode == TDOmode)
-	return N_("invalid conversion from type %<__dmr%>");
-      if (tomode == TDOmode)
-	return N_("invalid conversion to type %<__dmr%>");
     }
 
   /* Conversion allowed.  */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 67ef3d3a7d0..79ce1a8cbf1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -562,12 +562,6 @@ extern int rs6000_vector_align[];
 					 && TARGET_P8_VECTOR		\
 					 && TARGET_POWERPC64)
 
-/* Whether we have dense math support.  At present, we don't have a dense math
-   ISA bit, just use the future bit set by -mcpu=future.  */
-#define TARGET_DENSE_MATH		TARGET_FUTURE
-#define TARGET_MMA_DENSE_MATH		(TARGET_MMA && TARGET_DENSE_MATH)
-#define TARGET_MMA_NO_DENSE_MATH	(TARGET_MMA && !TARGET_DENSE_MATH)
-
 /* Inlining allows targets to define the meanings of bits in target_info
    field of ipa_fn_summary by itself, the used bits for rs6000 are listed
    below.  */
@@ -665,7 +659,6 @@ extern unsigned char rs6000_recip_bits[];
 #define UNITS_PER_FP_WORD 8
 #define UNITS_PER_ALTIVEC_WORD 16
 #define UNITS_PER_VSX_WORD 16
-#define UNITS_PER_DMR_WORD 128
 
 /* Type used for ptrdiff_t, as a string used in a declaration.  */
 #define PTRDIFF_TYPE "int"
@@ -793,7 +786,7 @@ enum data_align { align_abi, align_opt, align_both };
    Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
    pointer, which is eventually eliminated in favor of SP or FP.  */
 
-#define FIRST_PSEUDO_REGISTER 119
+#define FIRST_PSEUDO_REGISTER 111
 
 /* Use standard DWARF numbering for DWARF debugging information.  */
 #define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
@@ -830,9 +823,7 @@ enum data_align { align_abi, align_opt, align_both };
    /* cr0..cr7 */				   \
    0, 0, 0, 0, 0, 0, 0, 0,			   \
    /* vrsave vscr sfp */			   \
-   1, 1, 1,					   \
-   /* DMR registers.  */			   \
-   0, 0, 0, 0, 0, 0, 0, 0			   \
+   1, 1, 1					   \
 }
 
 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -856,9 +847,7 @@ enum data_align { align_abi, align_opt, align_both };
    /* cr0..cr7 */				   \
    1, 1, 0, 0, 0, 1, 1, 1,			   \
    /* vrsave vscr sfp */			   \
-   0, 0, 0,					   \
-   /* DMR registers.  */			   \
-   0, 0, 0, 0, 0, 0, 0, 0			   \
+   0, 0, 0					   \
 }
 
 #define TOTAL_ALTIVEC_REGS	(LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -895,7 +884,6 @@ enum data_align { align_abi, align_opt, align_both };
 	v2		(not saved; incoming vector arg reg; return value)
 	v19 - v14	(not saved or used for anything)
 	v31 - v20	(saved; order given to save least number)
-	dmr0 - dmr7	(not saved)
 	vrsave, vscr	(fixed)
 	sfp		(fixed)
 */
@@ -938,9 +926,6 @@ enum data_align { align_abi, align_opt, align_both };
    66,								\
    83, 82, 81, 80, 79, 78,					\
    95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84,		\
-   /* DMR registers.  */					\
-   111, 112, 113, 114, 115, 116, 117, 118,			\
-   /* Vrsave, vscr, sfp.  */					\
    108, 109,							\
    110								\
 }
@@ -967,9 +952,6 @@ enum data_align { align_abi, align_opt, align_both };
 /* True if register is a VSX register.  */
 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
 
-/* True if register is a DMR register.  */
-#define DMR_REGNO_P(N) ((N) >= FIRST_DMR_REGNO && (N) <= LAST_DMR_REGNO)
-
 /* Alternate name for any vector register supporting floating point, no matter
    which instruction set(s) are available.  */
 #define VFLOAT_REGNO_P(N) \
@@ -1009,7 +991,7 @@ enum data_align { align_abi, align_opt, align_both };
 /* Modes that are not vectors, but require vector alignment.  Treat these like
    vectors in terms of loads and stores.  */
 #define VECTOR_ALIGNMENT_P(MODE)					\
-  (FLOAT128_VECTOR_P (MODE) || OPAQUE_MODE_P (MODE))
+  (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode)
 
 #define ALTIVEC_VECTOR_MODE(MODE)					\
   ((MODE) == V16QImode							\
@@ -1105,7 +1087,6 @@ enum reg_class
   FLOAT_REGS,
   ALTIVEC_REGS,
   VSX_REGS,
-  DM_REGS,
   VRSAVE_REGS,
   VSCR_REGS,
   GEN_OR_FLOAT_REGS,
@@ -1135,7 +1116,6 @@ enum reg_class
   "FLOAT_REGS",								\
   "ALTIVEC_REGS",							\
   "VSX_REGS",								\
-  "DM_REGS",								\
   "VRSAVE_REGS",							\
   "VSCR_REGS",								\
   "GEN_OR_FLOAT_REGS",							\
@@ -1170,8 +1150,6 @@ enum reg_class
   { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 },			\
   /* VSX_REGS.  */							\
   { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 },			\
-  /* DM_REGS.  */							\
-  { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 },			\
   /* VRSAVE_REGS.  */							\
   { 0x00000000, 0x00000000, 0x00000000, 0x00001000 },			\
   /* VSCR_REGS.  */							\
@@ -1199,7 +1177,7 @@ enum reg_class
   /* CA_REGS.  */							\
   { 0x00000000, 0x00000000, 0x00000000, 0x00000004 },			\
   /* ALL_REGS.  */							\
-  { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff }			\
+  { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff }			\
 }
 
 /* The same information, inverted:
@@ -1223,7 +1201,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wr,		/* GPR register if 64-bit  */
   RS6000_CONSTRAINT_wx,		/* FPR register for STFIWX */
   RS6000_CONSTRAINT_wA,		/* BASE_REGS if 64-bit.  */
-  RS6000_CONSTRAINT_wD,		/* Accumulator regs if MMA/Dense Math.  */
   RS6000_CONSTRAINT_MAX
 };
 
@@ -2100,16 +2077,7 @@ extern char rs6000_reg_names[][8];	/* register names (0 vs. %r0).  */
   &rs6000_reg_names[108][0],	/* vrsave  */				\
   &rs6000_reg_names[109][0],	/* vscr  */				\
 									\
-  &rs6000_reg_names[110][0],	/* sfp  */				\
-									\
-  &rs6000_reg_names[111][0],	/* dmr0  */				\
-  &rs6000_reg_names[112][0],	/* dmr1  */				\
-  &rs6000_reg_names[113][0],	/* dmr2  */				\
-  &rs6000_reg_names[114][0],	/* dmr3  */				\
-  &rs6000_reg_names[115][0],	/* dmr4  */				\
-  &rs6000_reg_names[116][0],	/* dmr5  */				\
-  &rs6000_reg_names[117][0],	/* dmr6  */				\
-  &rs6000_reg_names[118][0],	/* dmr7  */				\
+  &rs6000_reg_names[110][0]	/* sfp  */				\
 }
 
 /* Table of additional register names to use in user input.  */
@@ -2163,8 +2131,6 @@ extern char rs6000_reg_names[][8];	/* register names (0 vs. %r0).  */
   {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87},	\
   {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91},	\
   {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95},	\
-  {"dmr0", 111}, {"dmr1", 112}, {"dmr2", 113}, {"dmr3", 114},	\
-  {"dmr4", 115}, {"dmr5", 116}, {"dmr6", 117}, {"dmr7", 118},	\
 }
 
 /* This is how to output an element of a case-vector that is relative.  */
@@ -2298,7 +2264,6 @@ enum rs6000_builtin_type_index
   RS6000_BTI_const_str,		 /* pointer to const char * */
   RS6000_BTI_vector_pair,	 /* unsigned 256-bit types (vector pair).  */
   RS6000_BTI_vector_quad,	 /* unsigned 512-bit types (vector quad).  */
-  RS6000_BTI_dmr,		 /* unsigned 1,024-bit types (dmr).  */
   RS6000_BTI_const_ptr_void,     /* const pointer to void */
   RS6000_BTI_ptr_V16QI,
   RS6000_BTI_ptr_V1TI,
@@ -2337,7 +2302,6 @@ enum rs6000_builtin_type_index
   RS6000_BTI_ptr_dfloat128,
   RS6000_BTI_ptr_vector_pair,
   RS6000_BTI_ptr_vector_quad,
-  RS6000_BTI_ptr_dmr,
   RS6000_BTI_ptr_long_long,
   RS6000_BTI_ptr_long_long_unsigned,
   RS6000_BTI_MAX
@@ -2395,7 +2359,6 @@ enum rs6000_builtin_type_index
 #define const_str_type_node		 (rs6000_builtin_types[RS6000_BTI_const_str])
 #define vector_pair_type_node		 (rs6000_builtin_types[RS6000_BTI_vector_pair])
 #define vector_quad_type_node		 (rs6000_builtin_types[RS6000_BTI_vector_quad])
-#define dmr_type_node			 (rs6000_builtin_types[RS6000_BTI_dmr])
 #define pcvoid_type_node		 (rs6000_builtin_types[RS6000_BTI_const_ptr_void])
 #define ptr_V16QI_type_node		 (rs6000_builtin_types[RS6000_BTI_ptr_V16QI])
 #define ptr_V1TI_type_node		 (rs6000_builtin_types[RS6000_BTI_ptr_V1TI])
@@ -2434,7 +2397,6 @@ enum rs6000_builtin_type_index
 #define ptr_dfloat128_type_node		 (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128])
 #define ptr_vector_pair_type_node	 (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair])
 #define ptr_vector_quad_type_node	 (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad])
-#define ptr_dmr_type_node		 (rs6000_builtin_types[RS6000_BTI_ptr_dmr])
 #define ptr_long_long_integer_type_node	 (rs6000_builtin_types[RS6000_BTI_ptr_long_long])
 #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned])
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2ccd83c9092..abc809448ad 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -51,8 +51,6 @@
    (VRSAVE_REGNO		108)
    (VSCR_REGNO			109)
    (FRAME_POINTER_REGNUM	110)
-   (FIRST_DMR_REGNO		111)
-   (LAST_DMR_REGNO		118)
   ])
 
 ;;
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ac68a8e1cb7..5730bda80dc 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3440,11 +3440,6 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.
 @item wA
 Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
 
-@item wD
-Accumulator register if @option{-mma} is used; otherwise,
-@code{NO_REGS}.  For @option{-mcpu=power10} the accumulator registers
-overlap with VSX vector registers 0..31.
-
 @item wB
 Signed 5-bit constant integer that can be loaded into an Altivec register.
 
diff --git a/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c b/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c
deleted file mode 100644
index 0a9884ddf63..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_dense_math_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-/* Test basic load/store for __dmr type.  */
-
-#ifndef CONSTRAINT
-#if defined(USE_D)
-#define CONSTRAINT "d"
-
-#elif defined(USE_V)
-#define CONSTRAINT "v"
-
-#elif defined(USE_WA)
-#define CONSTRAINT "wa"
-
-#else
-#define CONSTRAINT "wD"
-#endif
-#endif
-const char constraint[] = CONSTRAINT;
-
-void foo_mem_asm (__dmr *p, __dmr *q)
-{
-  /* 2 LXVP instructions.  */
-  __dmr vq = *p;
-
-  /* 2 DMXXINSTDMR512 instructions to transfer VSX to DMR.  */
-  __asm__ ("# foo (" CONSTRAINT ") %A0" : "+" CONSTRAINT (vq));
-  /* 2 DMXXEXTFDMR512 instructions to transfer DMR to VSX.  */
-
-  /* 2 STXVP instructions.  */
-  *q = vq;
-}
-
-void foo_mem_asm2 (__dmr *p, __dmr *q)
-{
-  /* 2 LXVP instructions.  */
-  __dmr vq = *p;
-  __dmr vq2;
-  __dmr vq3;
-
-  /* 2 DMXXINSTDMR512 instructions to transfer VSX to DMR.  */
-  __asm__ ("# foo1 (" CONSTRAINT ") %A0" : "+" CONSTRAINT (vq));
-  /* 2 DMXXEXTFDMR512 instructions to transfer DMR to VSX.  */
-
-  vq2 = vq;
-  __asm__ ("# foo2 (wa) %0" : "+wa" (vq2));
-
-  /* 2 STXVP instructions.  */
-  *q = vq2;
-}
-
-void foo_mem (__dmr *p, __dmr *q)
-{
-  /* 2 LXVP, 2 STXVP instructions, no DMR transfer.  */
-  *q = *p;
-}
-
-/* { dg-final { scan-assembler-times {\mdmxxextfdmr512\M}  4 } } */
-/* { dg-final { scan-assembler-times {\mdmxxinstdmr512\M}  4 } } */
-/* { dg-final { scan-assembler-times {\mlxvp\M}           12 } } */
-/* { dg-final { scan-assembler-times {\mstxvp\M}          12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
deleted file mode 100644
index 66c19779585..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/* Test derived from mma-double-1.c, modified for dense math.  */
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_dense_math_ok } */
-/* { dg-options "-mdejagnu-cpu=future -O2" } */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <altivec.h>
-
-typedef unsigned char vec_t __attribute__ ((vector_size (16)));
-typedef double v4sf_t __attribute__ ((vector_size (16)));
-#define SAVE_ACC(ACC, ldc, J)  \
-	  __builtin_mma_disassemble_acc (result, ACC); \
-	  rowC = (v4sf_t *) &CO[0*ldc+J]; \
-          rowC[0] += result[0]; \
-          rowC = (v4sf_t *) &CO[1*ldc+J]; \
-          rowC[0] += result[1]; \
-          rowC = (v4sf_t *) &CO[2*ldc+J]; \
-          rowC[0] += result[2]; \
-          rowC = (v4sf_t *) &CO[3*ldc+J]; \
-	  rowC[0] += result[3];
-
-void
-DM (int m, int n, int k, double *A, double *B, double *C)
-{
-  __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;
-  v4sf_t result[4];
-  v4sf_t *rowC;
-  for (int l = 0; l < n; l += 4)
-    {
-      double *CO;
-      double *AO;
-      AO = A;
-      CO = C;
-      C += m * 4;
-      for (int j = 0; j < m; j += 16)
-	{
-	  double *BO = B;
-	  __builtin_mma_xxsetaccz (&acc0);
-	  __builtin_mma_xxsetaccz (&acc1);
-	  __builtin_mma_xxsetaccz (&acc2);
-	  __builtin_mma_xxsetaccz (&acc3);
-	  __builtin_mma_xxsetaccz (&acc4);
-	  __builtin_mma_xxsetaccz (&acc5);
-	  __builtin_mma_xxsetaccz (&acc6);
-	  __builtin_mma_xxsetaccz (&acc7);
-	  unsigned long i;
-
-	  for (i = 0; i < k; i++)
-	    {
-	      vec_t *rowA = (vec_t *) & AO[i * 16];
-	      __vector_pair rowB;
-	      vec_t *rb = (vec_t *) & BO[i * 4];
-	      __builtin_mma_assemble_pair (&rowB, rb[1], rb[0]);
-	      __builtin_mma_xvf64gerpp (&acc0, rowB, rowA[0]);
-	      __builtin_mma_xvf64gerpp (&acc1, rowB, rowA[1]);
-	      __builtin_mma_xvf64gerpp (&acc2, rowB, rowA[2]);
-	      __builtin_mma_xvf64gerpp (&acc3, rowB, rowA[3]);
-	      __builtin_mma_xvf64gerpp (&acc4, rowB, rowA[4]);
-	      __builtin_mma_xvf64gerpp (&acc5, rowB, rowA[5]);
-	      __builtin_mma_xvf64gerpp (&acc6, rowB, rowA[6]);
-	      __builtin_mma_xvf64gerpp (&acc7, rowB, rowA[7]);
-	    }
-	  SAVE_ACC (&acc0, m, 0);
-	  SAVE_ACC (&acc2, m, 4);
-	  SAVE_ACC (&acc1, m, 2);
-	  SAVE_ACC (&acc3, m, 6);
-	  SAVE_ACC (&acc4, m, 8);
-	  SAVE_ACC (&acc6, m, 12);
-	  SAVE_ACC (&acc5, m, 10);
-	  SAVE_ACC (&acc7, m, 14);
-	  AO += k * 16;
-	  BO += k * 4;
-	  CO += 16;
-	}
-      B += k * 4;
-    }
-}
-
-void
-init (double *matrix, int row, int column)
-{
-  for (int j = 0; j < column; j++)
-    {
-      for (int i = 0; i < row; i++)
-	{
-	  matrix[j * row + i] = (i * 16 + 2 + j) / 0.123;
-	}
-    }
-}
-
-void
-init0 (double *matrix, double *matrix1, int row, int column)
-{
-  for (int j = 0; j < column; j++)
-    for (int i = 0; i < row; i++)
-      matrix[j * row + i] = matrix1[j * row + i] = 0;
-}
-
-
-void
-print (const char *name, const double *matrix, int row, int column)
-{
-  printf ("Matrix %s has %d rows and %d columns:\n", name, row, column);
-  for (int i = 0; i < row; i++)
-    {
-      for (int j = 0; j < column; j++)
-	{
-	  printf ("%f ", matrix[j * row + i]);
-	}
-      printf ("\n");
-    }
-  printf ("\n");
-}
-
-int
-main (int argc, char *argv[])
-{
-  int rowsA, colsB, common;
-  int i, j, k;
-  int ret = 0;
-
-  for (int t = 16; t <= 128; t += 16)
-    {
-      for (int t1 = 4; t1 <= 16; t1 += 4)
-	{
-	  rowsA = t;
-	  colsB = t1;
-	  common = 1;
-	  /* printf ("Running test for rows = %d,cols = %d\n", t, t1); */
-	  double A[rowsA * common];
-	  double B[common * colsB];
-	  double C[rowsA * colsB];
-	  double D[rowsA * colsB];
-
-
-	  init (A, rowsA, common);
-	  init (B, common, colsB);
-	  init0 (C, D, rowsA, colsB);
-	  DM (rowsA, colsB, common, A, B, C);
-
-	  for (i = 0; i < colsB; i++)
-	    {
-	      for (j = 0; j < rowsA; j++)
-		{
-		  D[i * rowsA + j] = 0;
-		  for (k = 0; k < common; k++)
-		    {
-		      D[i * rowsA + j] +=
-			A[k * rowsA + j] * B[k + common * i];
-		    }
-		}
-	    }
-	  for (i = 0; i < colsB; i++)
-	    {
-	      for (j = 0; j < rowsA; j++)
-		{
-		  for (k = 0; k < common; k++)
-		    {
-		      if (D[i * rowsA + j] != C[i * rowsA + j])
-			{
-			  printf ("Error %d,%d,%d\n",i,j,k);
-			  ret++;
-			}
-		    }
-		}
-	    }
-	  if (ret)
-	    {
-	      print ("A", A, rowsA, common);
-	      print ("B", B, common, colsB);
-	      print ("C", C, rowsA, colsB);
-	      print ("D", D, rowsA, colsB);
-	    }
-	}
-    }
-  
-#ifdef VERBOSE
-  if (ret)
-    printf ("DM double test fail: %d errors\n",ret);
-  else
-    printf ("DM double test success: 0 DM errors\n");
-#else
-  if (ret)
-    abort();
-#endif
-      
-  return ret;
-}
-
-/* { dg-final { scan-assembler {\mdmsetdmrz\M}      } } */
-/* { dg-final { scan-assembler {\mdmxvf64gerpp\M}   } } */
-/* { dg-final { scan-assembler {\mdmxxextfdmr512\M} } } */
-
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 2e5508505aa..be80494be80 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7121,29 +7121,6 @@ proc check_effective_target_power11_ok { } {
     }
 }
 
-# Return 1 if this is a PowerPC target supporting -mcpu=future which enables
-# the dense math operations.
-proc check_effective_target_powerpc_dense_math_ok { } {
-    if { ([istarget powerpc*-*-*]) } {
-	return [check_no_compiler_messages powerpc_dense_math_ok object {
-	    __vector_quad vq;
-	    int main (void) {
-		#ifndef __PPC_DMR__
-		#error "target does not have dense math support."
-		#else
-		/* Make sure we have dense math support.  */
-		  __vector_quad dmr;
-		  __asm__ ("dmsetaccz %A0" : "=wD" (dmr));
-		  vq = dmr;
-		#endif
-		return 0;
-	    }
-	} "-mcpu=future"]
-    } else {
-	return 0;
-    }
-}
-
 # Return 1 if this is a PowerPC target supporting -mfloat128 via either
 # software emulation on power7/power8 systems or hardware support on power9.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [gcc(refs/users/meissner/heads/work163-dmf)] Revert all changes
@ 2024-03-22  3:40 Michael Meissner
  0 siblings, 0 replies; 7+ messages in thread
From: Michael Meissner @ 2024-03-22  3:40 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:d49aa664ce768f629c858158eca406991a66da85

commit d49aa664ce768f629c858158eca406991a66da85
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 21 23:40:14 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/altivec.md | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index da5db49d3af..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,17 +1883,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; Future cpu adds a vector rotate left word variant
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_FUTURE"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2024-03-22 19:29 UTC | newest]

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