From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id AF5D63858D1E; Fri, 22 Mar 2024 19:29:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AF5D63858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1711135757; bh=YKQxEsNHA9IU86letL5QGxSc5K8Ri0rnRXp/mSns+DM=; h=From:To:Subject:Date:From; b=Xjd1RSO7dYGTCXrEMQrGGr016nFZsjTFVkM7oIgiO+Be6ih8HU8CsnmNhr1NE1A7L 7ewkyUb0o/P707huqoo6l405kacnfW8FjlIc4jFuVRm+I51oso8VMuaLyT5jloylhl BiMi1F4RhH4bSSK++sRStWZSTOugZvtniOH+04ZA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work163-dmf)] Add -mcpu=future2 X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work163-dmf X-Git-Oldrev: e8475d5df773c63e9eedfe4b877b089ba12ec08d X-Git-Newrev: 441bcaef7d1837656be62501fc6da6e0d97d07c7 Message-Id: <20240322192917.AF5D63858D1E@sourceware.org> Date: Fri, 22 Mar 2024 19:29:17 +0000 (GMT) List-Id: https://gcc.gnu.org/g:441bcaef7d1837656be62501fc6da6e0d97d07c7 commit 441bcaef7d1837656be62501fc6da6e0d97d07c7 Author: Michael Meissner Date: Fri Mar 22 15:23:22 2024 -0400 Add -mcpu=future2 2024-03-22 Michael Meissner gcc/ * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future2. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR_FUTURE2 if -mcpu=future. * config/rs6000/rs6000-cpus.def (ISA_FUTURE2_MASKS_SERVER): New macro. (POWERPC_MASKS): Add support for -mcpu=future2. (future2 processor): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mcpu=future2. * config/rs6000/rs6000.opt (-mfuture2): New internal option. gcc/testsuite/ * gcc.target/powerpc/xvrlw.c: New test. * lib/target-supports.exp (check_effective_target_powerpc_future2_ok): New effective target test. Diff: --- gcc/config/rs6000/aix71.h | 1 + gcc/config/rs6000/aix72.h | 1 + gcc/config/rs6000/aix73.h | 1 + gcc/config/rs6000/altivec.md | 14 +++++++++++++ gcc/config/rs6000/rs6000-c.cc | 2 ++ gcc/config/rs6000/rs6000-cpus.def | 5 +++++ gcc/config/rs6000/rs6000-tables.opt | 3 +++ gcc/config/rs6000/rs6000.cc | 1 + gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.opt | 4 ++++ gcc/testsuite/gcc.target/powerpc/xvrlw.c | 34 ++++++++++++++++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 13 ++++++++++++ 12 files changed, 80 insertions(+) diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 570ddcc451d..34bbad65dbe 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future2: -mfuture; \ mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index 242ca94bd06..f5e66084553 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future2: -mfuture; \ mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h index 2bd6b4bb3c4..1140f0f6098 100644 --- a/gcc/config/rs6000/aix73.h +++ b/gcc/config/rs6000/aix73.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future2: -mfuture; \ mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 4d4c94ff0a0..87fd3c5f3ef 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1883,6 +1883,20 @@ } [(set_attr "type" "vecperm")]) +;; -mcpu=future adds a vector rotate left word variant. There is no vector +;; byte/half-word/double-word/quad-word rotate left. This insn occurs before +;; altivec_vrl and will match for -mcpu=future, while other cpus will +;; match the generic insn. +(define_insn "*xvrlw" + [(set (match_operand:V4SI 0 "register_operand" "=v,wa") + (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa") + (match_operand:V4SI 2 "register_operand" "v,wa")))] + "TARGET_FUTURE2" + "@ + vrlw %0,%1,%2 + xvrlw %x0,%x1,%x2" + [(set_attr "type" "vecsimple")]) + (define_insn "altivec_vrl" [(set (match_operand:VI2 0 "register_operand" "=v") (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index acd44058876..f0461e5817a 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -451,6 +451,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); if ((flags & OPTION_MASK_FUTURE) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); + if ((flags & OPTION_MASK_FUTURE2) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE2"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 4ddba142e44..fee97c96197 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -93,6 +93,9 @@ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_FUTURE) +#define ISA_FUTURE2_MASKS_SERVER (ISA_FUTURE_MASKS_SERVER \ + | OPTION_MASK_FUTURE2) + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -133,6 +136,7 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ | OPTION_MASK_FUTURE \ + | OPTION_MASK_FUTURE2 \ | OPTION_MASK_POWER10 \ | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ @@ -269,3 +273,4 @@ RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER) RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER) +RS6000_CPU ("future2", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE2_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index f009c4e5718..291e295331e 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -203,3 +203,6 @@ Enum(rs6000_cpu_opt_value) String(power11) Value(57) EnumValue Enum(rs6000_cpu_opt_value) String(future) Value(58) +EnumValue +Enum(rs6000_cpu_opt_value) String(future2) Value(59) + diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 573602d0c11..42e9fa1dc56 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -24643,6 +24643,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "future", OPTION_MASK_FUTURE, false, false }, + { "future2", OPTION_MASK_FUTURE2, false, false }, { "power10", OPTION_MASK_POWER10, false, true }, { "power11", OPTION_MASK_POWER11, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 67ef3d3a7d0..7936c65d4ab 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -106,6 +106,7 @@ you make changes here, make them also there. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future2: -mfuture; \ mcpu=future: -mfuture; \ mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 621ebd65a88..97120a0b64b 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -587,6 +587,10 @@ Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpowe mfuture Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>) +;; Possible future bits beyound -mcpu=future +mfuture2 +Target Undocumented Mask(FUTURE2) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture2>) + mprefixed Target Mask(PREFIXED) Var(rs6000_isa_flags) Generate (do not generate) prefixed memory instructions. diff --git a/gcc/testsuite/gcc.target/powerpc/xvrlw.c b/gcc/testsuite/gcc.target/powerpc/xvrlw.c new file mode 100644 index 00000000000..f0a28a8a430 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/xvrlw.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_future2_ok } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test whether the xvrl (vector word rotate left using VSX registers insead of + Altivec registers is generated. */ + +#include + +typedef vector unsigned int v4si_t; + +v4si_t +rotl_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x << n) | (x >> (32 - n)); +} + +v4si_t +rotr_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x >> n) | (x << (32 - n)); +} + +v4si_t +rotl_v4si_vector (v4si_t x, v4si_t y) +{ + __asm__ (" # %x0" : "+f" (x)); + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times {\mxvrl\M} 3 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 9e765e21b1d..7f4617f27f2 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7133,6 +7133,19 @@ proc check_effective_target_powerpc_future_ok { } { } "-mcpu=future"] } +# Return 1 if this is a PowerPC target supporting -mcpu=future2 which enables +# potential instructins beyond -mcpu=future. Note, the assembler may not +# have support for these instructions. +proc check_effective_target_powerpc_future2_ok { } { + return [check_no_compiler_messages powerpc_future2_ok assembly { + #ifndef _ARCH_PWR_FUTURE2 + #error "-mcpu=future2 is not supported" + #else + int dummy; + #endif + } "-mcpu=future2"] +} + # Return 1 if this is a PowerPC target supporting -mcpu=future which enables # the dense math operations. proc check_effective_target_powerpc_dense_math_ok { } {