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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work164-dmf)] Revert all changes
Date: Tue, 9 Apr 2024 21:52:49 +0000 (GMT) [thread overview]
Message-ID: <20240409215249.A46343870C3B@sourceware.org> (raw)
https://gcc.gnu.org/g:91942e4a15ff9486fbabd14670c27b0addb07619
commit 91942e4a15ff9486fbabd14670c27b0addb07619
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 9 17:52:46 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/altivec.md | 14 -----
gcc/config/rs6000/constraints.md | 10 ----
gcc/config/rs6000/predicates.md | 52 +----------------
gcc/config/rs6000/rs6000.cc | 25 --------
gcc/config/rs6000/rs6000.h | 7 ---
gcc/config/rs6000/rs6000.md | 96 +++++--------------------------
gcc/testsuite/gcc.target/powerpc/paddis.c | 24 --------
gcc/testsuite/gcc.target/powerpc/xvrlw.c | 34 -----------
8 files changed, 14 insertions(+), 248 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index fd3397b16f6..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
}
[(set_attr "type" "vecperm")])
-;; -mcpu=future2 adds a vector rotate left word variant. There is no vector
-;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
- [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
- (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
- (match_operand:V4SI 2 "register_operand" "v,wa")))]
- "TARGET_XVRLW"
- "@
- vrlw %0,%1,%2
- xvrlw %x0,%x1,%x2"
- [(set_attr "type" "vecsimple")])
-
(define_insn "altivec_vrl<VI_char>"
[(set (match_operand:VI2 0 "register_operand" "=v")
(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 4d8d21fd6bb..277a30a8245 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,16 +222,6 @@
"An IEEE 128-bit constant that can be loaded into VSX registers."
(match_operand 0 "easy_vector_constant_ieee128"))
-(define_constraint "eU"
- "@internal integer constant that can be loaded with paddis"
- (and (match_code "const_int")
- (match_operand 0 "paddis_operand")))
-
-(define_constraint "eV"
- "@internal integer constant that can be loaded with paddis + paddi"
- (and (match_code "const_int")
- (match_operand 0 "paddis_paddi_operand")))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0b7c0bf4b0f..b325000690b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,53 +369,6 @@
return SIGNED_INTEGER_34BIT_P (INTVAL (op));
})
-;; Return 1 if op is a 64-bit constant that uses the paddis instruction
-(define_predicate "paddis_operand"
- (match_code "const_int")
-{
- if (!TARGET_PADDIS && TARGET_POWERPC64)
- return 0;
-
- /* If addi, addis, or paddi can handle the number, don't return true. */
- HOST_WIDE_INT value = INTVAL (op);
- if (SIGNED_INTEGER_34BIT_P (value))
- return false;
-
- /* If the number is too large for padds, return false. */
- if (!SIGNED_INTEGER_32BIT_P (value >> 32))
- return false;
-
- /* If the bottom 32-bits are non-zero, paddis can't handle it. */
- if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0)
- return false;
-
- return true;
-})
-
-;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
-;; addi/addis/paddi instruction combination.
-(define_predicate "paddis_paddi_operand"
- (match_code "const_int")
-{
- if (!TARGET_PADDIS && TARGET_POWERPC64)
- return 0;
-
- /* If addi, addis, or paddi can handle the number, don't return true. */
- HOST_WIDE_INT value = INTVAL (op);
- if (SIGNED_INTEGER_34BIT_P (value))
- return false;
-
- /* If the number is too large for padds, return false. */
- if (!SIGNED_INTEGER_32BIT_P (value >> 32))
- return false;
-
- /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */
- if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0)
- return false;
-
- return true;
-})
-
;; Return 1 if op is a register that is not special.
;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1097,10 +1050,7 @@
(if_then_else (match_code "const_int")
(match_test "satisfies_constraint_I (op)
|| satisfies_constraint_L (op)
- || satisfies_constraint_eI (op)
- || satisfies_constraint_eU (op)
- || satisfies_constraint_eV (op)")
-
+ || satisfies_constraint_eI (op)")
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 963c42df3d7..42e9fa1dc56 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4307,7 +4307,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_PCREL;
}
-
/* Print the options after updating the defaults. */
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
@@ -6118,14 +6117,6 @@ num_insns_constant_gpr (HOST_WIDE_INT value)
else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value))
return 1;
- /* PADDIS support. */
- else if (TARGET_PADDIS && TARGET_POWERPC64
- && !IN_RANGE (value >> 32, -1, 0)
- && (SIGNED_INTEGER_32BIT_P (value >> 32)))
- return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
- ? 1
- : 2);
-
else if (TARGET_POWERPC64)
{
int num_insns = 0;
@@ -6146,14 +6137,6 @@ num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
{
int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
int total = 0;
- if (nregs == 1
- && TARGET_PADDIS && TARGET_POWERPC64
- && !IN_RANGE (value >> 32, -1, 0)
- && SIGNED_INTEGER_32BIT_P (value >> 32))
- return ((value & HOST_WIDE_INT_C (0xffffffff)) == 0
- ? 1
- : 2);
-
while (nregs-- > 0)
{
HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
@@ -14228,14 +14211,6 @@ print_operand (FILE *file, rtx x, int code)
fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
return;
- case 'B':
- /* Upper 32-bits of a constant. */
- if (!CONST_INT_P (x))
- output_operand_lossage ("Not a constant.");
-
- fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32);
- return;
-
case 'D':
/* Like 'J' but get to the GT bit only. */
if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f52e0474e48..7936c65d4ab 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -574,12 +574,6 @@ extern int rs6000_vector_align[];
below. */
#define RS6000_FN_TARGET_INFO_HTM 1
-/* Whether we have PADDIS support. */
-#define TARGET_PADDIS TARGET_FUTURE2
-
-/* Whether we have XVRLW support. */
-#define TARGET_XVRLW TARGET_FUTURE2
-
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
@@ -2502,7 +2496,6 @@ typedef struct GTY(()) machine_function
(HOST_WIDE_INT_1 << ((N)-1)) - 1)
#define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16)
-#define SIGNED_INTEGER_32BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 32)
#define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34)
/* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f96a228d1ba..6fffc0db613 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -357,7 +357,7 @@
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,paddis"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -405,11 +405,6 @@
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
-
- (and (eq_attr "isa" "paddis")
- (match_test "TARGET_PADDIS"))
- (const_int 1)
-
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
@@ -1815,42 +1810,17 @@
})
(define_insn "*add<mode>3"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r,r,b")
- (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b,b,b")
- (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))]
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+ (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")
+ (match_operand:GPR 2 "add_operand" "r,I,L,eI")))]
""
"@
add %0,%1,%2
addi %0,%1,%2
addis %0,%1,%v2
- addi %0,%1,%2
- paddis %0,%1,%B2
- #"
+ addi %0,%1,%2"
[(set_attr "type" "add")
- (set_attr "isa" "*,*,*,p10,paddis,paddis")
- (set_attr "length" "*,*,*,*,12,24")
- (set_attr "prefixed" "*,*,*,*,yes,yes")
- (set_attr "maybe_prefixed" "*,*,*,*,no,no")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand")
- (plus:DI (match_operand:DI 1 "gpc_reg_operand")
- (match_operand:DI 2 "paddis_paddi_operand")))]
- "TARGET_PADDIS && TARGET_POWERPC64"
- [(set (match_dup 3)
- (plus:DI (match_dup 1)
- (match_dup 4)))
- (set (match_dup 0)
- (plus:DI (match_dup 3)
- (match_dup 5)))]
-{
- HOST_WIDE_INT value = INTVAL (operands[2]);
- operands[3] = (can_create_pseudo_p ()
- ? gen_reg_rtx (DImode)
- : operands[0]);
- operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
- operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
+ (set_attr "isa" "*,*,*,p10")])
(define_insn "*addsi3_high"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -9865,7 +9835,7 @@
DONE;
})
-;; GPR store GPR load GPR move GPR paddis GPR paddis+paddi
+;; GPR store GPR load GPR move
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9875,7 +9845,7 @@
;; VSX->GPR GPR->VSX
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=YZ, r, r, r, b,
+ "=YZ, r, r,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9884,7 +9854,7 @@
r, *h, *h,
?r, ?wa")
(match_operand:DI 1 "input_operand"
- "r, YZ, r, eU, eV,
+ "r, YZ, r,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9899,8 +9869,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- paddis %0,0,%B1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9926,7 +9894,7 @@
mfvsrd %0,%x1
mtvsrd %x0,%1"
[(set_attr "type"
- "store, load, *, *, *,
+ "store, load, *,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9936,7 +9904,7 @@
mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "length"
- "*, *, *, 12, 24,
+ "*, *, *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9945,32 +9913,14 @@
*, *, *,
*, *")
(set_attr "isa"
- "*, *, *, paddis, paddis,
+ "*, *, *,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *,
p7v, p7v,
*, *, *,
- p8v, p8v")
- (set_attr "prefixed"
- "*, *, *, yes, yes,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *,
- *, *, *,
- *, *")
- (set_attr "maybe_prefixed"
- "*, *, *, no, no,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *,
- *, *, *,
- *, *")])
+ p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
; instruction.
@@ -9988,26 +9938,6 @@
(match_dup 1)))]
"")
-;; Split a constant that can be generated by a paddis and paddi into 2
-;; instructions.
-(define_split
- [(set (match_operand:DI 0 "int_reg_operand")
- (match_operand:DI 1 "paddis_paddi_operand"))]
- "TARGET_PADDIS && TARGET_POWERPC64"
- [(set (match_dup 2)
- (match_dup 3))
- (set (match_dup 0)
- (plus:DI (match_dup 2)
- (match_dup 4)))]
-{
- HOST_WIDE_INT value = INTVAL (operands[1]);
- operands[2] = (can_create_pseudo_p ()
- ? gen_reg_rtx (DImode)
- : operands[0]);
- operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff));
- operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff));
-})
-
;; Split a load of a large constant into the appropriate five-instruction
;; sequence. Handle anything in a constant number of insns.
;; When non-easy constants can go in the TOC, this should use
diff --git a/gcc/testsuite/gcc.target/powerpc/paddis.c b/gcc/testsuite/gcc.target/powerpc/paddis.c
deleted file mode 100644
index bdf0fdbddf6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/paddis.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future2 -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
- Altivec registers is generated. */
-
-#include <stddef.h>
-
-size_t
-prefix_addis_addi (size_t x)
-{
- return x + 0x123456789ABCDEUL;
-}
-
-size_t
-prefix_addis (size_t x)
-{
- return x + 0x12345600000000UL;
-}
-
-/* { dg-final { scan-assembler-times {\mpaddis\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/xvrlw.c b/gcc/testsuite/gcc.target/powerpc/xvrlw.c
deleted file mode 100644
index 846f2e337c5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/xvrlw.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future2 -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
- Altivec registers is generated. */
-
-#include <altivec.h>
-
-typedef vector unsigned int v4si_t;
-
-v4si_t
-rotl_v4si_scalar (v4si_t x, unsigned long n)
-{
- __asm__ (" # %x0" : "+f" (x));
- return (x << n) | (x >> (32 - n));
-}
-
-v4si_t
-rotr_v4si_scalar (v4si_t x, unsigned long n)
-{
- __asm__ (" # %x0" : "+f" (x));
- return (x >> n) | (x << (32 - n));
-}
-
-v4si_t
-rotl_v4si_vector (v4si_t x, v4si_t y)
-{
- __asm__ (" # %x0" : "+f" (x));
- return vec_rl (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mxvrl\M} 3 } } */
next reply other threads:[~2024-04-09 21:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-09 21:52 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2024-04-09 23:12 Michael Meissner
2024-04-08 23:25 Michael Meissner
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