[gcc(refs/users/meissner/heads/work164-dmf)] Revert all changes

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:2c5222ca63b78a756e294a45f58806552d1d6d79

commit 2c5222ca63b78a756e294a45f58806552d1d6d79
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 9 19:12:48 2024 -0400

    Revert all changes

Diff:
---
 gcc/config/rs6000/altivec.md                       | 14 ---------
 gcc/config/rs6000/rs6000.h                         |  3 --
 .../gcc.target/powerpc/vector-rotate-left.c        | 34 ----------------------
 3 files changed, 51 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index fd3397b16f6..4d4c94ff0a0 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,20 +1883,6 @@
 }
   [(set_attr "type" "vecperm")])
 
-;; -mcpu=future2 adds a vector rotate left word variant.  There is no vector
-;; byte/half-word/double-word/quad-word rotate left.  This insn occurs before
-;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will
-;; match the generic insn.
-(define_insn "*xvrlw"
-  [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
-	(rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
-		     (match_operand:V4SI 2 "register_operand" "v,wa")))]
-  "TARGET_XVRLW"
-  "@
-   vrlw %0,%1,%2
-   xvrlw %x0,%x1,%x2"
-  [(set_attr "type" "vecsimple")])
-
 (define_insn "altivec_vrl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f52e0474e48..37afa67f184 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -577,9 +577,6 @@ extern int rs6000_vector_align[];
 /* Whether we have PADDIS support.  */
 #define TARGET_PADDIS			TARGET_FUTURE2
 
-/* Whether we have XVRLW support.  */
-#define TARGET_XVRLW			TARGET_FUTURE2
-
 /* Whether the various reciprocal divide/square root estimate instructions
    exist, and whether we should automatically generate code for the instruction
    by default.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
deleted file mode 100644
index 846f2e337c5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_future2_ok } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=future2 -O2" } */
-
-/* Test whether the xvrl (vector word rotate left using VSX registers insead of
-   Altivec registers is generated.  */
-
-#include <altivec.h>
-
-typedef vector unsigned int  v4si_t;
-
-v4si_t
-rotl_v4si_scalar (v4si_t x, unsigned long n)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return (x << n) | (x >> (32 - n));
-}
-
-v4si_t
-rotr_v4si_scalar (v4si_t x, unsigned long n)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return (x >> n) | (x << (32 - n));
-}
-
-v4si_t
-rotl_v4si_vector (v4si_t x, v4si_t y)
-{
-  __asm__ (" # %x0" : "+f" (x));
-  return vec_rl (x, y);
-}
-
-/* { dg-final { scan-assembler-times {\mxvrl\M} 3  } } */