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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.* Date: Fri, 12 Apr 2024 18:39:06 +0000 (GMT) [thread overview] Message-ID: <20240412183906.6134C3858C50@sourceware.org> (raw) https://gcc.gnu.org/g:87d20d149ee92ba3ba0415299eae6dce12482bec commit 87d20d149ee92ba3ba0415299eae6dce12482bec Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Apr 12 14:39:02 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 1b5fe755ae5..ed1739ca4df 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -7,12 +7,17 @@ Simplify converting between SImode and SF/DFmode. gcc/ PR target/90822 - * gcc/config/rs6000.md (floatsidf2): If SImode can live in the floating - point registers, directly issue a conversion to DImode and do the - floating point conversion. + * gcc/config/rs6000.md (uns code attribute): Add sign_extend and + zero_extend. + (floatsidf2): If SImode can live in the floating point registers, + directly issue a conversion to DImode and do the floating point + conversion during expansion instead of using an UNSPEC. (floatunssisf2): Likewise. (floatunssidf2): Likewise. (floatsisf2): Likewise. + * gcc/config/rs6000/vsx.md (vsx_extract_si_<uns>float_df): Adjust + combiner to expect sign/zero extend of SImode to DImode in optimizing + V4SI extracts. ==================== Branch work164-bugs, patch #205 ====================
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