From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2017) id D52DA3858D32; Mon, 15 Apr 2024 13:12:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D52DA3858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713186745; bh=ZEziJnXpxgm7dFlCuLH8IbPaO4uUVvyaJ7qeeb6xQJc=; h=From:To:Subject:Date:From; b=ISqzzK67iAqkr9rEU8+lY7gAbPGtvrXFGtPCpLY3HWoj8Ro2Dlmobyj+vf8vafMM7 UE9sZL54d18awnTYWFEh53ByapA20nAbAKmQm3g6og+6vEMuOUR5SVPLRIy32Y0B1v nKT/wH0VU7mwAhpAseU83/AU8sRrlXzZRAhaEOJ8= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Robin Dapp To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-9972] RISC-V: Add VLS to mask vec_extract [PR114668]. X-Act-Checkin: gcc X-Git-Author: Robin Dapp X-Git-Refname: refs/heads/master X-Git-Oldrev: 9d573f71e80e9f6f4aac912fc8fc128aa2697e3a X-Git-Newrev: 02cc8f3e68f9af96d484d9946ceaa9e3eed38151 Message-Id: <20240415131225.D52DA3858D32@sourceware.org> Date: Mon, 15 Apr 2024 13:12:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:02cc8f3e68f9af96d484d9946ceaa9e3eed38151 commit r14-9972-g02cc8f3e68f9af96d484d9946ceaa9e3eed38151 Author: Robin Dapp Date: Mon Apr 15 12:44:56 2024 +0200 RISC-V: Add VLS to mask vec_extract [PR114668]. This adds the missing VLS modes to the mask extract expanders. gcc/ChangeLog: PR target/114668 * config/riscv/autovec.md: Add VLS. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114668.c: New test. Diff: --- gcc/config/riscv/autovec.md | 4 +-- .../gcc.target/riscv/rvv/autovec/pr114668.c | 35 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 3b32369f68c..aa1ae0fe075 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1427,7 +1427,7 @@ (define_expand "vec_extractqi" [(set (match_operand:QI 0 "register_operand") (vec_select:QI - (match_operand:VB 1 "register_operand") + (match_operand:VB_VLS 1 "register_operand") (parallel [(match_operand 2 "nonmemory_operand")])))] "TARGET_VECTOR" @@ -1453,7 +1453,7 @@ (define_expand "vec_extractbi" [(set (match_operand:QI 0 "register_operand") (vec_select:QI - (match_operand:VB 1 "register_operand") + (match_operand:VB_VLS 1 "register_operand") (parallel [(match_operand 2 "nonmemory_operand")])))] "TARGET_VECTOR" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c new file mode 100644 index 00000000000..3a13c3c0012 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114668.c @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v } */ +/* { dg-options { -O3 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d } } */ + +char a; +int b; +short e[14]; +char f[4][12544]; +_Bool c[4][5]; + +__attribute__ ((noipa)) +void foo (int a) +{ + if (a != 1) + __builtin_abort (); +} + +int main () +{ + for (int i = 0; i < 4; ++i) + for (int l = 0; l < 15; ++l) + for (int m = 0; m < 15; ++m) + f[i][l * m] = 3; + for (int j = 0; j < 4; j += 1) + for (int k = 3; k < 13; k += 3) + for (_Bool l = 0; l < 1; l = 1) + for (int m = 0; m < 4; m += 1) + { + a = 0; + b -= e[k]; + c[j][m] = f[j][6]; + } + for (long i = 2; i < 4; ++i) + foo (c[3][3]); +}