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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*
X-Act-Checkin: gcc
X-Git-Author: Michael Meissner <meissner@linux.ibm.com>
X-Git-Refname: refs/users/meissner/heads/work164-test
X-Git-Oldrev: 3212394be5a6ade7b60a0d126e7dcadee8a04fb2
X-Git-Newrev: 4b2a63df76b9046fd770e2748e9bd281c3becff1
Message-Id: <20240415204608.604CF3858D32@sourceware.org>
Date: Mon, 15 Apr 2024 20:46:08 +0000 (GMT)
List-Id: <gcc-cvs.sourceware.org>

https://gcc.gnu.org/g:4b2a63df76b9046fd770e2748e9bd281c3becff1

commit 4b2a63df76b9046fd770e2748e9bd281c3becff1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Apr 15 16:46:05 2024 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 8b12e86f37b..fd5e9d14a39 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,28 @@
+==================== Branch work164-test, patch #303 ====================
+
+Update TAR support.
+
+2024-04-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/rs6000.cc (rs6000_debug_reg_global): Correctly print TAR
+	register.
+	(rs6000_init_hard_regno_mode_ok): Correctly initial TAR register.
+	* config/rs6000/rs6000.md (mov<mode>_internal): Add support for TAR
+	register.
+	(movcc_<mode>): Likewise.
+	(movsf_hardfloat): Likewise.
+	(movsf_hardfloat): Likewise.
+	(movsd_hardfloat): Likewise.
+	(mov<mode>_hardfloat64): Likewise.
+	(mov<mode>_softfloat6): Likewise.
+	(indirect_jump): Likewise.
+	(@indirect_jump<mode>_nospec): Likewise.
+	(<bd>tf_<mode>): Remove TAR register.
+	* lra-constraints.cc (lra_constraints): Add debug_rtx before raising an
+	error.
+
 ==================== Branch work164-test, patch #302 ====================
 
 Remove moves for tar register.