From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7942) id A44DE3858D32; Tue, 16 Apr 2024 05:29:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A44DE3858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713245364; bh=rmQ0Jd5JFkZnrdmuZ+qrOLt1qTrOodqI05X4B181W7w=; h=From:To:Subject:Date:From; b=F0nPGKi9V2qoTWa6P2IXaZSpoVqp5Bjw6jqh63nDIdetJ1Plk79t21BudxGB5IDm5 MDkUjtB+YAiftkwb3307ItU5sla2hZKjHkyS7DrzfwA2TyP8tScJqbrTbdowjvCMDQ ud517MhWa7X4jBtdLBVBZd1DCB8z6safw2Xnx9VE= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Fei Gao To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-9986] optimize Zicond conditional select cases. X-Act-Checkin: gcc X-Git-Author: Fei Gao X-Git-Refname: refs/heads/master X-Git-Oldrev: c39dc5bb65c492fafc5a0fde83708b8d24e0338d X-Git-Newrev: 6e925ba0a8b9619ed789a456b087755b488d66f1 Message-Id: <20240416052924.A44DE3858D32@sourceware.org> Date: Tue, 16 Apr 2024 05:29:24 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6e925ba0a8b9619ed789a456b087755b488d66f1 commit r14-9986-g6e925ba0a8b9619ed789a456b087755b488d66f1 Author: Fei Gao Date: Mon Apr 15 06:33:17 2024 +0000 optimize Zicond conditional select cases. When one of the two input operands is 0, ADD and IOR are functionally equivalent. ADD is slightly preferred over IOR because ADD has a higher likelihood of being implemented as a compressed instruction when compared to IOR. C.ADD uses the CR format with any of the 32 RVI registers availble, while C.OR uses the CA format with limit to just 8 of them. Conditional select, if zero case: rd = (rc == 0) ? rs1 : rs2 before patch: czero.nez rd, rs1, rc czero.eqz rtmp, rs2, rc or rd, rd, rtmp after patch: czero.eqz rd, rs1, rc czero.nez rtmp, rs2, rc add rd, rd, rtmp Same trick applies for the conditional select, if non-zero case: rd = (rc != 0) ? rs1 : rs2 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): replace or with add when expanding zicond if possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-prefer-add-to-or.c: New test. Diff: --- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 74445bc977c..0519e0679ed 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4709,7 +4709,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) gen_rtx_IF_THEN_ELSE (mode, cond1, CONST0_RTX (mode), alt))); - riscv_emit_binary (IOR, dest, reg1, reg2); + riscv_emit_binary (PLUS, dest, reg1, reg2); return true; } } diff --git a/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c new file mode 100644 index 00000000000..f3f7beb0b5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */ + +long cond_select_if_zero(long a, long b, long c) { + return a == 0 ? c : b; +} + +long cond_select_if_non_zero(long a, long b, long c) { + return a != 0 ? c : b; +} + +/* { dg-final { scan-assembler-times {add\t} 2 } } */ +/* { dg-final { scan-assembler-not {or\t} } } */ +