[gcc r14-10050] RISC-V: Add xfail test case for wv insn register overlap

[Pan Li <panli@gcc.gnu.org>]

https://gcc.gnu.org/g:9f10005dbc9b660465ec4a9640bcbdcc1e5171c3

commit r14-10050-g9f10005dbc9b660465ec4a9640bcbdcc1e5171c3
Author: Pan Li <pan2.li@intel.com>
Date:   Sat Apr 20 09:02:39 2024 +0800

    RISC-V: Add xfail test case for wv insn register overlap
    
    We reverted below patch for wv insn overlap, add the related wv
    insn test and mark it as xfail.  And we will remove the xfail
    after we support the register overlap in GCC-15.
    
    b3b2799b872 RISC-V: Support one more overlap for wv instructions
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/pr112431-42.c: New test.
    
    Signed-off-by: Pan Li <pan2.li@intel.com>

Diff:
---
 .../gcc.target/riscv/rvv/base/pr112431-42.c        | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
new file mode 100644
index 00000000000..fa5dac58a20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+int64_t
+reduc_plus_int (int *__restrict a, int n)
+{
+  int64_t r = 0;
+  for (int i = 0; i < n; ++i)
+    r += a[i];
+  return r;
+}
+
+double
+reduc_plus_float (float *__restrict a, int n)
+{
+  double r = 0;
+  for (int i = 0; i < n; ++i)
+    r += a[i];
+  return r;
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-assembler-times {vwadd\.wv} 1 } } */
+/* { dg-final { scan-assembler-times {vfwadd\.wv} 1 } } */