From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 2AF2B3858D3C; Sun, 21 Apr 2024 01:37:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2AF2B3858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713663433; bh=Ws76YupphNqGX2haFvqKPXO638RNm2bxUwFuf9cyyWI=; h=From:To:Subject:Date:From; b=tXI6tp79xIWpA8VwQWmaDiPwz2rg1PJUDfG4P79Pkcru0o+1/wEu0r5enAFebSMJS cqILZVQdxRd3qr0bZ3MN+Lzh9KzE3oX0UaiCtfmUvuxdSq+HMqRtr5CJSOqPf8TYv1 rra5JWo/jsQxmsZtEyE+rBZ1seI//jKTyBZz5OZk= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-10057] Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions" X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: d37b34fe82e6e19e80ec9c46400f63fa90ba5255 X-Git-Newrev: ef2392236ec629351496d7f299d6a0956080e4d9 Message-Id: <20240421013713.2AF2B3858D3C@sourceware.org> Date: Sun, 21 Apr 2024 01:37:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ef2392236ec629351496d7f299d6a0956080e4d9 commit r14-10057-gef2392236ec629351496d7f299d6a0956080e4d9 Author: Pan Li Date: Sun Apr 21 09:37:00 2024 +0800 Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions" This reverts commit a23415d7572774701d7ec04664390260ab9a3f63. Diff: --- gcc/config/riscv/vector.md | 65 ++++--- .../gcc.target/riscv/rvv/base/pr112431-22.c | 188 --------------------- .../gcc.target/riscv/rvv/base/pr112431-23.c | 119 ------------- .../gcc.target/riscv/rvv/base/pr112431-24.c | 86 ---------- .../gcc.target/riscv/rvv/base/pr112431-25.c | 104 ------------ .../gcc.target/riscv/rvv/base/pr112431-26.c | 68 -------- .../gcc.target/riscv/rvv/base/pr112431-27.c | 51 ------ 7 files changed, 31 insertions(+), 650 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 2a6ab979588..f620f13682c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3818,28 +3818,27 @@ (set_attr "mode" "")]) (define_insn "@pred_dual_widen__scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTI (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" " vr, vr")) (any_extend:VWEXTI (vec_duplicate: - (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "reg_or_0_operand" " rJ, rJ")))) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vw.vx\t%0,%3,%z4%p1" [(set_attr "type" "vi") - (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "mode" "")]) (define_insn "@pred_single_widen_sub" [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") @@ -3928,28 +3927,27 @@ (set_attr "mode" "")]) (define_insn "@pred_widen_mulsu_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (mult:VWEXTI (sign_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" " vr, vr")) (zero_extend:VWEXTI (vec_duplicate: - (match_operand: 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "reg_or_0_operand" " rJ, rJ")))) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vwmulsu.vx\t%0,%3,%z4%p1" [(set_attr "type" "viwmul") - (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "mode" "")]) ;; vwcvt.x.x.v (define_insn "@pred_" @@ -7113,32 +7111,31 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_dual_widen__scalar" - [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (any_widen_binop:VWEXTF (float_extend:VWEXTF - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) + (match_operand: 3 "register_operand" " vr, vr")) (float_extend:VWEXTF (vec_duplicate: - (match_operand: 4 "register_operand" " f, f, f, f, f, f, f, f")))) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 4 "register_operand" " f, f")))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[9])")) - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen_add" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c deleted file mode 100644 index 90db18217bb..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c +++ /dev/null @@ -1,188 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, - size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, - size_t sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m2_t vw0 = __riscv_vwadd_vx_i16m2 (v0, 33, vl); - vint16m2_t vw1 = __riscv_vwadd_vx_i16m2 (v1, 33, vl); - vint16m2_t vw2 = __riscv_vwadd_vx_i16m2 (v2, 33, vl); - vint16m2_t vw3 = __riscv_vwadd_vx_i16m2 (v3, 33, vl); - vint16m2_t vw4 = __riscv_vwadd_vx_i16m2 (v4, 33, vl); - vint16m2_t vw5 = __riscv_vwadd_vx_i16m2 (v5, 33, vl); - vint16m2_t vw6 = __riscv_vwadd_vx_i16m2 (v6, 33, vl); - vint16m2_t vw7 = __riscv_vwadd_vx_i16m2 (v7, 33, vl); - vint16m2_t vw8 = __riscv_vwadd_vx_i16m2 (v8, 33, vl); - vint16m2_t vw9 = __riscv_vwadd_vx_i16m2 (v9, 33, vl); - vint16m2_t vw10 = __riscv_vwadd_vx_i16m2 (v10, 33, vl); - vint16m2_t vw11 = __riscv_vwadd_vx_i16m2 (v11, 33, vl); - vint16m2_t vw12 = __riscv_vwadd_vx_i16m2 (v12, 33, vl); - vint16m2_t vw13 = __riscv_vwadd_vx_i16m2 (v13, 33, vl); - vint16m2_t vw14 = __riscv_vwadd_vx_i16m2 (v14, 33, vl); - vint16m2_t vw15 = __riscv_vwadd_vx_i16m2 (v15, 33, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7); - size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8); - size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9); - size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10); - size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11); - size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12); - size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13); - size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14); - size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -size_t -foo2 (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m2_t vw0 = __riscv_vwmulsu_vx_i16m2 (v0, 33, vl); - vint16m2_t vw1 = __riscv_vwmulsu_vx_i16m2 (v1, 33, vl); - vint16m2_t vw2 = __riscv_vwmulsu_vx_i16m2 (v2, 33, vl); - vint16m2_t vw3 = __riscv_vwmulsu_vx_i16m2 (v3, 33, vl); - vint16m2_t vw4 = __riscv_vwmulsu_vx_i16m2 (v4, 33, vl); - vint16m2_t vw5 = __riscv_vwmulsu_vx_i16m2 (v5, 33, vl); - vint16m2_t vw6 = __riscv_vwmulsu_vx_i16m2 (v6, 33, vl); - vint16m2_t vw7 = __riscv_vwmulsu_vx_i16m2 (v7, 33, vl); - vint16m2_t vw8 = __riscv_vwmulsu_vx_i16m2 (v8, 33, vl); - vint16m2_t vw9 = __riscv_vwmulsu_vx_i16m2 (v9, 33, vl); - vint16m2_t vw10 = __riscv_vwmulsu_vx_i16m2 (v10, 33, vl); - vint16m2_t vw11 = __riscv_vwmulsu_vx_i16m2 (v11, 33, vl); - vint16m2_t vw12 = __riscv_vwmulsu_vx_i16m2 (v12, 33, vl); - vint16m2_t vw13 = __riscv_vwmulsu_vx_i16m2 (v13, 33, vl); - vint16m2_t vw14 = __riscv_vwmulsu_vx_i16m2 (v14, 33, vl); - vint16m2_t vw15 = __riscv_vwmulsu_vx_i16m2 (v15, 33, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7); - size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8); - size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9); - size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10); - size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11); - size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12); - size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13); - size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14); - size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c deleted file mode 100644 index ee0b928e9df..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c +++ /dev/null @@ -1,119 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v4 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v5 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v6 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v7 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m4_t vw0 = __riscv_vwadd_vx_i16m4 (v0, 55, vl); - vint16m4_t vw1 = __riscv_vwadd_vx_i16m4 (v1, 55, vl); - vint16m4_t vw2 = __riscv_vwadd_vx_i16m4 (v2, 55, vl); - vint16m4_t vw3 = __riscv_vwadd_vx_i16m4 (v3, 55, vl); - vint16m4_t vw4 = __riscv_vwadd_vx_i16m4 (v4, 55, vl); - vint16m4_t vw5 = __riscv_vwadd_vx_i16m4 (v5, 55, vl); - vint16m4_t vw6 = __riscv_vwadd_vx_i16m4 (v6, 55, vl); - vint16m4_t vw7 = __riscv_vwadd_vx_i16m4 (v7, 55, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m4_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m4_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m4_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m4_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m4_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m4_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m4_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m4_i16 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -size_t -foo2 (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v4 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v5 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v6 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v7 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m4_t vw0 = __riscv_vwmulsu_vx_i16m4 (v0, 55, vl); - vint16m4_t vw1 = __riscv_vwmulsu_vx_i16m4 (v1, 55, vl); - vint16m4_t vw2 = __riscv_vwmulsu_vx_i16m4 (v2, 55, vl); - vint16m4_t vw3 = __riscv_vwmulsu_vx_i16m4 (v3, 55, vl); - vint16m4_t vw4 = __riscv_vwmulsu_vx_i16m4 (v4, 55, vl); - vint16m4_t vw5 = __riscv_vwmulsu_vx_i16m4 (v5, 55, vl); - vint16m4_t vw6 = __riscv_vwmulsu_vx_i16m4 (v6, 55, vl); - vint16m4_t vw7 = __riscv_vwmulsu_vx_i16m4 (v7, 55, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m4_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m4_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m4_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m4_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m4_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m4_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m4_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m4_i16 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c deleted file mode 100644 index 603e2941cd3..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c +++ /dev/null @@ -1,86 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m4_t v0 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v1 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v2 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v3 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m8_t vw0 = __riscv_vwadd_vx_i16m8 (v0, 66, vl); - vint16m8_t vw1 = __riscv_vwadd_vx_i16m8 (v1, 66, vl); - vint16m8_t vw2 = __riscv_vwadd_vx_i16m8 (v2, 66, vl); - vint16m8_t vw3 = __riscv_vwadd_vx_i16m8 (v3, 66, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m8_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m8_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m8_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m8_i16 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -size_t -foo2 (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m4_t v0 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v1 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v2 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v3 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m8_t vw0 = __riscv_vwmulsu_vx_i16m8 (v0, 66, vl); - vint16m8_t vw1 = __riscv_vwmulsu_vx_i16m8 (v1, 66, vl); - vint16m8_t vw2 = __riscv_vwmulsu_vx_i16m8 (v2, 66, vl); - vint16m8_t vw3 = __riscv_vwmulsu_vx_i16m8 (v3, 66, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m8_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m8_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m8_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m8_i16 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c deleted file mode 100644 index 0b52b9f24eb..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c +++ /dev/null @@ -1,104 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, - size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, - size_t sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v4 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v5 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v6 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v7 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v8 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v9 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v10 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v11 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v12 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v13 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v14 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v15 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m2_t vw0 = __riscv_vfwadd_vf_f64m2 (v0, 33, vl); - vfloat64m2_t vw1 = __riscv_vfwadd_vf_f64m2 (v1, 33, vl); - vfloat64m2_t vw2 = __riscv_vfwadd_vf_f64m2 (v2, 33, vl); - vfloat64m2_t vw3 = __riscv_vfwadd_vf_f64m2 (v3, 33, vl); - vfloat64m2_t vw4 = __riscv_vfwadd_vf_f64m2 (v4, 33, vl); - vfloat64m2_t vw5 = __riscv_vfwadd_vf_f64m2 (v5, 33, vl); - vfloat64m2_t vw6 = __riscv_vfwadd_vf_f64m2 (v6, 33, vl); - vfloat64m2_t vw7 = __riscv_vfwadd_vf_f64m2 (v7, 33, vl); - vfloat64m2_t vw8 = __riscv_vfwadd_vf_f64m2 (v8, 33, vl); - vfloat64m2_t vw9 = __riscv_vfwadd_vf_f64m2 (v9, 33, vl); - vfloat64m2_t vw10 = __riscv_vfwadd_vf_f64m2 (v10, 33, vl); - vfloat64m2_t vw11 = __riscv_vfwadd_vf_f64m2 (v11, 33, vl); - vfloat64m2_t vw12 = __riscv_vfwadd_vf_f64m2 (v12, 33, vl); - vfloat64m2_t vw13 = __riscv_vfwadd_vf_f64m2 (v13, 33, vl); - vfloat64m2_t vw14 = __riscv_vfwadd_vf_f64m2 (v14, 33, vl); - vfloat64m2_t vw15 = __riscv_vfwadd_vf_f64m2 (v15, 33, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vfmv_f_s_f64m2_f64 (vw0); - size_t sum1 = __riscv_vfmv_f_s_f64m2_f64 (vw1); - size_t sum2 = __riscv_vfmv_f_s_f64m2_f64 (vw2); - size_t sum3 = __riscv_vfmv_f_s_f64m2_f64 (vw3); - size_t sum4 = __riscv_vfmv_f_s_f64m2_f64 (vw4); - size_t sum5 = __riscv_vfmv_f_s_f64m2_f64 (vw5); - size_t sum6 = __riscv_vfmv_f_s_f64m2_f64 (vw6); - size_t sum7 = __riscv_vfmv_f_s_f64m2_f64 (vw7); - size_t sum8 = __riscv_vfmv_f_s_f64m2_f64 (vw8); - size_t sum9 = __riscv_vfmv_f_s_f64m2_f64 (vw9); - size_t sum10 = __riscv_vfmv_f_s_f64m2_f64 (vw10); - size_t sum11 = __riscv_vfmv_f_s_f64m2_f64 (vw11); - size_t sum12 = __riscv_vfmv_f_s_f64m2_f64 (vw12); - size_t sum13 = __riscv_vfmv_f_s_f64m2_f64 (vw13); - size_t sum14 = __riscv_vfmv_f_s_f64m2_f64 (vw14); - size_t sum15 = __riscv_vfmv_f_s_f64m2_f64 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c deleted file mode 100644 index d21a73765ed..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c +++ /dev/null @@ -1,68 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m2_t v0 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v1 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v2 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v3 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v4 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v5 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v6 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v7 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m4_t vw0 = __riscv_vfwadd_vf_f64m4 (v0, 33, vl); - vfloat64m4_t vw1 = __riscv_vfwadd_vf_f64m4 (v1, 33, vl); - vfloat64m4_t vw2 = __riscv_vfwadd_vf_f64m4 (v2, 33, vl); - vfloat64m4_t vw3 = __riscv_vfwadd_vf_f64m4 (v3, 33, vl); - vfloat64m4_t vw4 = __riscv_vfwadd_vf_f64m4 (v4, 33, vl); - vfloat64m4_t vw5 = __riscv_vfwadd_vf_f64m4 (v5, 33, vl); - vfloat64m4_t vw6 = __riscv_vfwadd_vf_f64m4 (v6, 33, vl); - vfloat64m4_t vw7 = __riscv_vfwadd_vf_f64m4 (v7, 33, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vfmv_f_s_f64m4_f64 (vw0); - size_t sum1 = __riscv_vfmv_f_s_f64m4_f64 (vw1); - size_t sum2 = __riscv_vfmv_f_s_f64m4_f64 (vw2); - size_t sum3 = __riscv_vfmv_f_s_f64m4_f64 (vw3); - size_t sum4 = __riscv_vfmv_f_s_f64m4_f64 (vw4); - size_t sum5 = __riscv_vfmv_f_s_f64m4_f64 (vw5); - size_t sum6 = __riscv_vfmv_f_s_f64m4_f64 (vw6); - size_t sum7 = __riscv_vfmv_f_s_f64m4_f64 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c deleted file mode 100644 index 2423f7b33ee..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m4_t v0 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - vfloat32m4_t v1 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - vfloat32m4_t v2 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - vfloat32m4_t v3 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m8_t vw0 = __riscv_vfwadd_vf_f64m8 (v0, 33, vl); - vfloat64m8_t vw1 = __riscv_vfwadd_vf_f64m8 (v1, 33, vl); - vfloat64m8_t vw2 = __riscv_vfwadd_vf_f64m8 (v2, 33, vl); - vfloat64m8_t vw3 = __riscv_vfwadd_vf_f64m8 (v3, 33, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vfmv_f_s_f64m8_f64 (vw0); - size_t sum1 = __riscv_vfmv_f_s_f64m8_f64 (vw1); - size_t sum2 = __riscv_vfmv_f_s_f64m8_f64 (vw2); - size_t sum3 = __riscv_vfmv_f_s_f64m8_f64 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */