From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 556C6384AB78; Mon, 22 Apr 2024 08:26:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 556C6384AB78 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713774374; bh=OO3PEZL0ME8Dl4bmd9SsWBL/jghECB9pqUvtWoBl7+s=; h=From:To:Subject:Date:From; b=AOwtvwRJlQ/5O1SpFKjzoa9Pgbry+1f00h6DmEbo1RTtsa/uRIC2kZ3CTziXcgo+f md2I3a+PP/e2Rx8e8YyMoMdpy+/e/b+l5/2ZPmde1Zm+L4E2stSuTXVrhjK8wjEMBL RFp6vCUyw/yfPXDp+VH1gAXFPlxpoTEgF4lUit3g= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-10069] Revert "RISC-V: Support highpart overlap for floating-point widen instructions" X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: a367b99f916cb7d2d673180ace640096fd118950 X-Git-Newrev: 4df96b4ec788f2d588febf3555685f2700b932b3 Message-Id: <20240422082614.556C6384AB78@sourceware.org> Date: Mon, 22 Apr 2024 08:26:14 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4df96b4ec788f2d588febf3555685f2700b932b3 commit r14-10069-g4df96b4ec788f2d588febf3555685f2700b932b3 Author: Pan Li Date: Mon Apr 22 16:25:57 2024 +0800 Revert "RISC-V: Support highpart overlap for floating-point widen instructions" This reverts commit 8614cbb253484e28c3eb20cde4d1067aad56de58. Diff: --- gcc/config/riscv/vector.md | 78 ++++----- .../gcc.target/riscv/rvv/base/pr112431-10.c | 104 ------------ .../gcc.target/riscv/rvv/base/pr112431-11.c | 68 -------- .../gcc.target/riscv/rvv/base/pr112431-12.c | 51 ------ .../gcc.target/riscv/rvv/base/pr112431-13.c | 188 --------------------- .../gcc.target/riscv/rvv/base/pr112431-14.c | 119 ------------- .../gcc.target/riscv/rvv/base/pr112431-15.c | 86 ---------- .../gcc.target/riscv/rvv/base/pr112431-7.c | 106 ------------ .../gcc.target/riscv/rvv/base/pr112431-8.c | 68 -------- .../gcc.target/riscv/rvv/base/pr112431-9.c | 51 ------ 10 files changed, 37 insertions(+), 882 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 768d23e9f1d..598aa8fba33 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7696,88 +7696,84 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_fcvt_x_f" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWCONVERTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec:VWCONVERTI - [(match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] VFCVTS) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + [(match_operand: 3 "register_operand" " vr, vr")] VFCVTS) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "") (set (attr "frm_mode") - (symbol_ref "riscv_vector::get_frm_mode (operands[8])")) - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) (define_insn "@pred_widen_" - [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr") (if_then_else:VWCONVERTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_fix:VWCONVERTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.rtz.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") - (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "mode" "")]) (define_insn "@pred_widen_" - [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, &vr") (if_then_else:V_VLSF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:V_VLSF - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfwcvtitof") - (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "mode" "")]) (define_insn "@pred_extend" - [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=&vr, &vr") (if_then_else:VWEXTF_ZVFHMIN (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (float_extend:VWEXTF_ZVFHMIN - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") - (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "mode" "")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point narrow conversions diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c deleted file mode 100644 index 5f161b31fa1..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c +++ /dev/null @@ -1,104 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3, double sum4, - double sum5, double sum6, double sum7, double sum8, double sum9, - double sum10, double sum11, double sum12, double sum13, double sum14, - double sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint32m1_t v0 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v1 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v2 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v3 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v4 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v5 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v6 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v7 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v8 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v9 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v10 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v11 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v12 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v13 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v14 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - vint32m1_t v15 = __riscv_vle32_v_i32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m2_t vw0 = __riscv_vfwcvt_f_x_v_f64m2 (v0, vl); - vfloat64m2_t vw1 = __riscv_vfwcvt_f_x_v_f64m2 (v1, vl); - vfloat64m2_t vw2 = __riscv_vfwcvt_f_x_v_f64m2 (v2, vl); - vfloat64m2_t vw3 = __riscv_vfwcvt_f_x_v_f64m2 (v3, vl); - vfloat64m2_t vw4 = __riscv_vfwcvt_f_x_v_f64m2 (v4, vl); - vfloat64m2_t vw5 = __riscv_vfwcvt_f_x_v_f64m2 (v5, vl); - vfloat64m2_t vw6 = __riscv_vfwcvt_f_x_v_f64m2 (v6, vl); - vfloat64m2_t vw7 = __riscv_vfwcvt_f_x_v_f64m2 (v7, vl); - vfloat64m2_t vw8 = __riscv_vfwcvt_f_x_v_f64m2 (v8, vl); - vfloat64m2_t vw9 = __riscv_vfwcvt_f_x_v_f64m2 (v9, vl); - vfloat64m2_t vw10 = __riscv_vfwcvt_f_x_v_f64m2 (v10, vl); - vfloat64m2_t vw11 = __riscv_vfwcvt_f_x_v_f64m2 (v11, vl); - vfloat64m2_t vw12 = __riscv_vfwcvt_f_x_v_f64m2 (v12, vl); - vfloat64m2_t vw13 = __riscv_vfwcvt_f_x_v_f64m2 (v13, vl); - vfloat64m2_t vw14 = __riscv_vfwcvt_f_x_v_f64m2 (v14, vl); - vfloat64m2_t vw15 = __riscv_vfwcvt_f_x_v_f64m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vfmv_f_s_f64m2_f64 (vw0); - double sum1 = __riscv_vfmv_f_s_f64m2_f64 (vw1); - double sum2 = __riscv_vfmv_f_s_f64m2_f64 (vw2); - double sum3 = __riscv_vfmv_f_s_f64m2_f64 (vw3); - double sum4 = __riscv_vfmv_f_s_f64m2_f64 (vw4); - double sum5 = __riscv_vfmv_f_s_f64m2_f64 (vw5); - double sum6 = __riscv_vfmv_f_s_f64m2_f64 (vw6); - double sum7 = __riscv_vfmv_f_s_f64m2_f64 (vw7); - double sum8 = __riscv_vfmv_f_s_f64m2_f64 (vw8); - double sum9 = __riscv_vfmv_f_s_f64m2_f64 (vw9); - double sum10 = __riscv_vfmv_f_s_f64m2_f64 (vw10); - double sum11 = __riscv_vfmv_f_s_f64m2_f64 (vw11); - double sum12 = __riscv_vfmv_f_s_f64m2_f64 (vw12); - double sum13 = __riscv_vfmv_f_s_f64m2_f64 (vw13); - double sum14 = __riscv_vfmv_f_s_f64m2_f64 (vw14); - double sum15 = __riscv_vfmv_f_s_f64m2_f64 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c deleted file mode 100644 index 82827d14e34..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c +++ /dev/null @@ -1,68 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3, double sum4, - double sum5, double sum6, double sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint32m2_t v0 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v1 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v2 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v3 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v4 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v5 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v6 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - vint32m2_t v7 = __riscv_vle32_v_i32m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m4_t vw0 = __riscv_vfwcvt_f_x_v_f64m4 (v0, vl); - vfloat64m4_t vw1 = __riscv_vfwcvt_f_x_v_f64m4 (v1, vl); - vfloat64m4_t vw2 = __riscv_vfwcvt_f_x_v_f64m4 (v2, vl); - vfloat64m4_t vw3 = __riscv_vfwcvt_f_x_v_f64m4 (v3, vl); - vfloat64m4_t vw4 = __riscv_vfwcvt_f_x_v_f64m4 (v4, vl); - vfloat64m4_t vw5 = __riscv_vfwcvt_f_x_v_f64m4 (v5, vl); - vfloat64m4_t vw6 = __riscv_vfwcvt_f_x_v_f64m4 (v6, vl); - vfloat64m4_t vw7 = __riscv_vfwcvt_f_x_v_f64m4 (v7, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vfmv_f_s_f64m4_f64 (vw0); - double sum1 = __riscv_vfmv_f_s_f64m4_f64 (vw1); - double sum2 = __riscv_vfmv_f_s_f64m4_f64 (vw2); - double sum3 = __riscv_vfmv_f_s_f64m4_f64 (vw3); - double sum4 = __riscv_vfmv_f_s_f64m4_f64 (vw4); - double sum5 = __riscv_vfmv_f_s_f64m4_f64 (vw5); - double sum6 = __riscv_vfmv_f_s_f64m4_f64 (vw6); - double sum7 = __riscv_vfmv_f_s_f64m4_f64 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c deleted file mode 100644 index c4ae60755ea..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint32m4_t v0 = __riscv_vle32_v_i32m4 ((void *) it, vl); - it += vl; - vint32m4_t v1 = __riscv_vle32_v_i32m4 ((void *) it, vl); - it += vl; - vint32m4_t v2 = __riscv_vle32_v_i32m4 ((void *) it, vl); - it += vl; - vint32m4_t v3 = __riscv_vle32_v_i32m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m8_t vw0 = __riscv_vfwcvt_f_x_v_f64m8 (v0, vl); - vfloat64m8_t vw1 = __riscv_vfwcvt_f_x_v_f64m8 (v1, vl); - vfloat64m8_t vw2 = __riscv_vfwcvt_f_x_v_f64m8 (v2, vl); - vfloat64m8_t vw3 = __riscv_vfwcvt_f_x_v_f64m8 (v3, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vfmv_f_s_f64m8_f64 (vw0); - double sum1 = __riscv_vfmv_f_s_f64m8_f64 (vw1); - double sum2 = __riscv_vfmv_f_s_f64m8_f64 (vw2); - double sum3 = __riscv_vfmv_f_s_f64m8_f64 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c deleted file mode 100644 index fde7076d34f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c +++ /dev/null @@ -1,188 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3, double sum4, - double sum5, double sum6, double sum7, double sum8, double sum9, - double sum10, double sum11, double sum12, double sum13, double sum14, - double sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v4 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v5 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v6 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v7 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v8 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v9 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v10 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v11 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v12 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v13 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v14 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v15 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint64m2_t vw0 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v0, vl); - vint64m2_t vw1 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v1, vl); - vint64m2_t vw2 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v2, vl); - vint64m2_t vw3 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v3, vl); - vint64m2_t vw4 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v4, vl); - vint64m2_t vw5 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v5, vl); - vint64m2_t vw6 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v6, vl); - vint64m2_t vw7 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v7, vl); - vint64m2_t vw8 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v8, vl); - vint64m2_t vw9 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v9, vl); - vint64m2_t vw10 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v10, vl); - vint64m2_t vw11 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v11, vl); - vint64m2_t vw12 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v12, vl); - vint64m2_t vw13 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v13, vl); - vint64m2_t vw14 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v14, vl); - vint64m2_t vw15 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vmv_x_s_i64m2_i64 (vw0); - double sum1 = __riscv_vmv_x_s_i64m2_i64 (vw1); - double sum2 = __riscv_vmv_x_s_i64m2_i64 (vw2); - double sum3 = __riscv_vmv_x_s_i64m2_i64 (vw3); - double sum4 = __riscv_vmv_x_s_i64m2_i64 (vw4); - double sum5 = __riscv_vmv_x_s_i64m2_i64 (vw5); - double sum6 = __riscv_vmv_x_s_i64m2_i64 (vw6); - double sum7 = __riscv_vmv_x_s_i64m2_i64 (vw7); - double sum8 = __riscv_vmv_x_s_i64m2_i64 (vw8); - double sum9 = __riscv_vmv_x_s_i64m2_i64 (vw9); - double sum10 = __riscv_vmv_x_s_i64m2_i64 (vw10); - double sum11 = __riscv_vmv_x_s_i64m2_i64 (vw11); - double sum12 = __riscv_vmv_x_s_i64m2_i64 (vw12); - double sum13 = __riscv_vmv_x_s_i64m2_i64 (vw13); - double sum14 = __riscv_vmv_x_s_i64m2_i64 (vw14); - double sum15 = __riscv_vmv_x_s_i64m2_i64 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -double -foo2 (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v4 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v5 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v6 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v7 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v8 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v9 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v10 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v11 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v12 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v13 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v14 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v15 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint64m2_t vw0 = __riscv_vfwcvt_x_f_v_i64m2 (v0, vl); - vint64m2_t vw1 = __riscv_vfwcvt_x_f_v_i64m2 (v1, vl); - vint64m2_t vw2 = __riscv_vfwcvt_x_f_v_i64m2 (v2, vl); - vint64m2_t vw3 = __riscv_vfwcvt_x_f_v_i64m2 (v3, vl); - vint64m2_t vw4 = __riscv_vfwcvt_x_f_v_i64m2 (v4, vl); - vint64m2_t vw5 = __riscv_vfwcvt_x_f_v_i64m2 (v5, vl); - vint64m2_t vw6 = __riscv_vfwcvt_x_f_v_i64m2 (v6, vl); - vint64m2_t vw7 = __riscv_vfwcvt_x_f_v_i64m2 (v7, vl); - vint64m2_t vw8 = __riscv_vfwcvt_x_f_v_i64m2 (v8, vl); - vint64m2_t vw9 = __riscv_vfwcvt_x_f_v_i64m2 (v9, vl); - vint64m2_t vw10 = __riscv_vfwcvt_x_f_v_i64m2 (v10, vl); - vint64m2_t vw11 = __riscv_vfwcvt_x_f_v_i64m2 (v11, vl); - vint64m2_t vw12 = __riscv_vfwcvt_x_f_v_i64m2 (v12, vl); - vint64m2_t vw13 = __riscv_vfwcvt_x_f_v_i64m2 (v13, vl); - vint64m2_t vw14 = __riscv_vfwcvt_x_f_v_i64m2 (v14, vl); - vint64m2_t vw15 = __riscv_vfwcvt_x_f_v_i64m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vmv_x_s_i64m2_i64 (vw0); - double sum1 = __riscv_vmv_x_s_i64m2_i64 (vw1); - double sum2 = __riscv_vmv_x_s_i64m2_i64 (vw2); - double sum3 = __riscv_vmv_x_s_i64m2_i64 (vw3); - double sum4 = __riscv_vmv_x_s_i64m2_i64 (vw4); - double sum5 = __riscv_vmv_x_s_i64m2_i64 (vw5); - double sum6 = __riscv_vmv_x_s_i64m2_i64 (vw6); - double sum7 = __riscv_vmv_x_s_i64m2_i64 (vw7); - double sum8 = __riscv_vmv_x_s_i64m2_i64 (vw8); - double sum9 = __riscv_vmv_x_s_i64m2_i64 (vw9); - double sum10 = __riscv_vmv_x_s_i64m2_i64 (vw10); - double sum11 = __riscv_vmv_x_s_i64m2_i64 (vw11); - double sum12 = __riscv_vmv_x_s_i64m2_i64 (vw12); - double sum13 = __riscv_vmv_x_s_i64m2_i64 (vw13); - double sum14 = __riscv_vmv_x_s_i64m2_i64 (vw14); - double sum15 = __riscv_vmv_x_s_i64m2_i64 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-14.c deleted file mode 100644 index 535ea7ce34b..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-14.c +++ /dev/null @@ -1,119 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3, double sum4, - double sum5, double sum6, double sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v4 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v5 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v6 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v7 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint64m2_t vw0 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v0, vl); - vint64m2_t vw1 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v1, vl); - vint64m2_t vw2 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v2, vl); - vint64m2_t vw3 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v3, vl); - vint64m2_t vw4 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v4, vl); - vint64m2_t vw5 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v5, vl); - vint64m2_t vw6 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v6, vl); - vint64m2_t vw7 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v7, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vmv_x_s_i64m2_i64 (vw0); - double sum1 = __riscv_vmv_x_s_i64m2_i64 (vw1); - double sum2 = __riscv_vmv_x_s_i64m2_i64 (vw2); - double sum3 = __riscv_vmv_x_s_i64m2_i64 (vw3); - double sum4 = __riscv_vmv_x_s_i64m2_i64 (vw4); - double sum5 = __riscv_vmv_x_s_i64m2_i64 (vw5); - double sum6 = __riscv_vmv_x_s_i64m2_i64 (vw6); - double sum7 = __riscv_vmv_x_s_i64m2_i64 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -double -foo2 (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v4 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v5 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v6 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v7 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint64m2_t vw0 = __riscv_vfwcvt_x_f_v_i64m2 (v0, vl); - vint64m2_t vw1 = __riscv_vfwcvt_x_f_v_i64m2 (v1, vl); - vint64m2_t vw2 = __riscv_vfwcvt_x_f_v_i64m2 (v2, vl); - vint64m2_t vw3 = __riscv_vfwcvt_x_f_v_i64m2 (v3, vl); - vint64m2_t vw4 = __riscv_vfwcvt_x_f_v_i64m2 (v4, vl); - vint64m2_t vw5 = __riscv_vfwcvt_x_f_v_i64m2 (v5, vl); - vint64m2_t vw6 = __riscv_vfwcvt_x_f_v_i64m2 (v6, vl); - vint64m2_t vw7 = __riscv_vfwcvt_x_f_v_i64m2 (v7, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vmv_x_s_i64m2_i64 (vw0); - double sum1 = __riscv_vmv_x_s_i64m2_i64 (vw1); - double sum2 = __riscv_vmv_x_s_i64m2_i64 (vw2); - double sum3 = __riscv_vmv_x_s_i64m2_i64 (vw3); - double sum4 = __riscv_vmv_x_s_i64m2_i64 (vw4); - double sum5 = __riscv_vmv_x_s_i64m2_i64 (vw5); - double sum6 = __riscv_vmv_x_s_i64m2_i64 (vw6); - double sum7 = __riscv_vmv_x_s_i64m2_i64 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-15.c deleted file mode 100644 index 3d46e4a829a..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-15.c +++ /dev/null @@ -1,86 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint64m2_t vw0 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v0, vl); - vint64m2_t vw1 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v1, vl); - vint64m2_t vw2 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v2, vl); - vint64m2_t vw3 = __riscv_vfwcvt_rtz_x_f_v_i64m2 (v3, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vmv_x_s_i64m2_i64 (vw0); - double sum1 = __riscv_vmv_x_s_i64m2_i64 (vw1); - double sum2 = __riscv_vmv_x_s_i64m2_i64 (vw2); - double sum3 = __riscv_vmv_x_s_i64m2_i64 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -double -foo2 (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint64m2_t vw0 = __riscv_vfwcvt_x_f_v_i64m2 (v0, vl); - vint64m2_t vw1 = __riscv_vfwcvt_x_f_v_i64m2 (v1, vl); - vint64m2_t vw2 = __riscv_vfwcvt_x_f_v_i64m2 (v2, vl); - vint64m2_t vw3 = __riscv_vfwcvt_x_f_v_i64m2 (v3, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vmv_x_s_i64m2_i64 (vw0); - double sum1 = __riscv_vmv_x_s_i64m2_i64 (vw1); - double sum2 = __riscv_vmv_x_s_i64m2_i64 (vw2); - double sum3 = __riscv_vmv_x_s_i64m2_i64 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c deleted file mode 100644 index 7064471496c..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c +++ /dev/null @@ -1,106 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3, double sum4, - double sum5, double sum6, double sum7, double sum8, double sum9, - double sum10, double sum11, double sum12, double sum13, double sum14, - double sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m1_t v0 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v1 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v2 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v3 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v4 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v5 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v6 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v7 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v8 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v9 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v10 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v11 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v12 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v13 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v14 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - vfloat32m1_t v15 = __riscv_vle32_v_f32m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m2_t vw0 = __riscv_vfwcvt_f_f_v_f64m2 (v0, vl); - vfloat64m2_t vw1 = __riscv_vfwcvt_f_f_v_f64m2 (v1, vl); - vfloat64m2_t vw2 = __riscv_vfwcvt_f_f_v_f64m2 (v2, vl); - vfloat64m2_t vw3 = __riscv_vfwcvt_f_f_v_f64m2 (v3, vl); - vfloat64m2_t vw4 = __riscv_vfwcvt_f_f_v_f64m2 (v4, vl); - vfloat64m2_t vw5 = __riscv_vfwcvt_f_f_v_f64m2 (v5, vl); - vfloat64m2_t vw6 = __riscv_vfwcvt_f_f_v_f64m2 (v6, vl); - vfloat64m2_t vw7 = __riscv_vfwcvt_f_f_v_f64m2 (v7, vl); - vfloat64m2_t vw8 = __riscv_vfwcvt_f_f_v_f64m2 (v8, vl); - vfloat64m2_t vw9 = __riscv_vfwcvt_f_f_v_f64m2 (v9, vl); - vfloat64m2_t vw10 = __riscv_vfwcvt_f_f_v_f64m2 (v10, vl); - vfloat64m2_t vw11 = __riscv_vfwcvt_f_f_v_f64m2 (v11, vl); - vfloat64m2_t vw12 = __riscv_vfwcvt_f_f_v_f64m2 (v12, vl); - vfloat64m2_t vw13 = __riscv_vfwcvt_f_f_v_f64m2 (v13, vl); - vfloat64m2_t vw14 = __riscv_vfwcvt_f_f_v_f64m2 (v14, vl); - vfloat64m2_t vw15 = __riscv_vfwcvt_f_f_v_f64m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vfmv_f_s_f64m2_f64 (vw0); - double sum1 = __riscv_vfmv_f_s_f64m2_f64 (vw1); - double sum2 = __riscv_vfmv_f_s_f64m2_f64 (vw2); - double sum3 = __riscv_vfmv_f_s_f64m2_f64 (vw3); - double sum4 = __riscv_vfmv_f_s_f64m2_f64 (vw4); - double sum5 = __riscv_vfmv_f_s_f64m2_f64 (vw5); - double sum6 = __riscv_vfmv_f_s_f64m2_f64 (vw6); - double sum7 = __riscv_vfmv_f_s_f64m2_f64 (vw7); - double sum8 = __riscv_vfmv_f_s_f64m2_f64 (vw8); - double sum9 = __riscv_vfmv_f_s_f64m2_f64 (vw9); - double sum10 = __riscv_vfmv_f_s_f64m2_f64 (vw10); - double sum11 = __riscv_vfmv_f_s_f64m2_f64 (vw11); - double sum12 = __riscv_vfmv_f_s_f64m2_f64 (vw12); - double sum13 = __riscv_vfmv_f_s_f64m2_f64 (vw13); - double sum14 = __riscv_vfmv_f_s_f64m2_f64 (vw14); - double sum15 = __riscv_vfmv_f_s_f64m2_f64 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ - - diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c deleted file mode 100644 index ab56d0d69af..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c +++ /dev/null @@ -1,68 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3, double sum4, - double sum5, double sum6, double sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m2_t v0 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v1 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v2 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v3 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v4 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v5 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v6 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - vfloat32m2_t v7 = __riscv_vle32_v_f32m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m4_t vw0 = __riscv_vfwcvt_f_f_v_f64m4 (v0, vl); - vfloat64m4_t vw1 = __riscv_vfwcvt_f_f_v_f64m4 (v1, vl); - vfloat64m4_t vw2 = __riscv_vfwcvt_f_f_v_f64m4 (v2, vl); - vfloat64m4_t vw3 = __riscv_vfwcvt_f_f_v_f64m4 (v3, vl); - vfloat64m4_t vw4 = __riscv_vfwcvt_f_f_v_f64m4 (v4, vl); - vfloat64m4_t vw5 = __riscv_vfwcvt_f_f_v_f64m4 (v5, vl); - vfloat64m4_t vw6 = __riscv_vfwcvt_f_f_v_f64m4 (v6, vl); - vfloat64m4_t vw7 = __riscv_vfwcvt_f_f_v_f64m4 (v7, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vfmv_f_s_f64m4_f64 (vw0); - double sum1 = __riscv_vfmv_f_s_f64m4_f64 (vw1); - double sum2 = __riscv_vfmv_f_s_f64m4_f64 (vw2); - double sum3 = __riscv_vfmv_f_s_f64m4_f64 (vw3); - double sum4 = __riscv_vfmv_f_s_f64m4_f64 (vw4); - double sum5 = __riscv_vfmv_f_s_f64m4_f64 (vw5); - double sum6 = __riscv_vfmv_f_s_f64m4_f64 (vw6); - double sum7 = __riscv_vfmv_f_s_f64m4_f64 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c deleted file mode 100644 index 82f369c0cd9..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -double __attribute__ ((noinline)) -sumation (double sum0, double sum1, double sum2, double sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -double -foo (char const *buf, size_t len) -{ - double sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vfloat32m4_t v0 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - vfloat32m4_t v1 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - vfloat32m4_t v2 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - vfloat32m4_t v3 = __riscv_vle32_v_f32m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vfloat64m8_t vw0 = __riscv_vfwcvt_f_f_v_f64m8 (v0, vl); - vfloat64m8_t vw1 = __riscv_vfwcvt_f_f_v_f64m8 (v1, vl); - vfloat64m8_t vw2 = __riscv_vfwcvt_f_f_v_f64m8 (v2, vl); - vfloat64m8_t vw3 = __riscv_vfwcvt_f_f_v_f64m8 (v3, vl); - - asm volatile("nop" ::: "memory"); - double sum0 = __riscv_vfmv_f_s_f64m8_f64 (vw0); - double sum1 = __riscv_vfmv_f_s_f64m8_f64 (vw1); - double sum2 = __riscv_vfmv_f_s_f64m8_f64 (vw2); - double sum3 = __riscv_vfmv_f_s_f64m8_f64 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */