From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 2FC533858D38; Mon, 22 Apr 2024 12:46:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2FC533858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713789960; bh=duK6eDMYdedawSUGmemYcCPPOP+G2lbZcGz1uMKsdIo=; h=From:To:Subject:Date:From; b=fVM5ewkWg+Igpqb9j8/cZRmP2n2AW4b1i6THTkfEbDSWebRi92FNoM8RdG3qWCwtY Flq6k7EqJc0jsx5qHxxyEq9dp6Mo1W6k2qQEAcOuVhE8wI6ShYa7CorLPwZyhhkKtJ TLM7vDCxtIZD8Q1pDAIDYx5aWNCQ+FwzM9laayTU= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-10074] Revert "RISC-V: Rename vconstraint into group_overlap" X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: b78c88438cf3672987736edc013ffc0b20e879f7 X-Git-Newrev: cacc55a4c0be8d0bc7417b6a28924eadbbe428e3 Message-Id: <20240422124600.2FC533858D38@sourceware.org> Date: Mon, 22 Apr 2024 12:46:00 +0000 (GMT) List-Id: https://gcc.gnu.org/g:cacc55a4c0be8d0bc7417b6a28924eadbbe428e3 commit r14-10074-gcacc55a4c0be8d0bc7417b6a28924eadbbe428e3 Author: Pan Li Date: Mon Apr 22 20:45:40 2024 +0800 Revert "RISC-V: Rename vconstraint into group_overlap" This reverts commit e65aaf8efe1900f7bbf76235a078000bf2ec8b45. Diff: --- gcc/config/riscv/constraints.md | 12 ++++++------ gcc/config/riscv/riscv.md | 19 ++++++++----------- gcc/config/riscv/vector.md | 4 ++-- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 972e8842c9f..e37c6936bfa 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -173,14 +173,14 @@ (define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS" "A vector register has register number % 8 == 4." "regno % 8 == 4") -(define_register_constraint "W43" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 4 == 3." "regno % 4 == 3") +(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 4 == 1." "regno % 4 == 1") -(define_register_constraint "W86" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 6." "regno % 8 == 6") +(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 8 == 1." "regno % 8 == 1") -(define_register_constraint "W87" "TARGET_VECTOR ? V_REGS : NO_REGS" - "A vector register has register number % 8 == 7." "regno % 8 == 7") +(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register has register number % 8 == 2." "regno % 8 == 2") ;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov". ;; VLENB is a run-time constant which represent the vector register length in bytes. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3628e2215da..1693d4008c6 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -538,25 +538,22 @@ ] (const_string "no"))) -;; Widening instructions have group-overlap constraints. Those are only -;; valid for certain register-group sizes. This attribute marks the -;; alternatives not matching the required register-group size as disabled. -(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87" - (const_string "none")) +(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82" + (const_string "no")) -(define_attr "group_overlap_valid" "no,yes" - (cond [(eq_attr "group_overlap" "none") +(define_attr "vconstraint_enabled" "no,yes" + (cond [(eq_attr "vconstraint" "no") (const_string "yes") - (and (eq_attr "group_overlap" "W21") + (and (eq_attr "vconstraint" "W21") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2")) (const_string "no") - (and (eq_attr "group_overlap" "W42,W43") + (and (eq_attr "vconstraint" "W42,W41") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4")) (const_string "no") - (and (eq_attr "group_overlap" "W84,W86,W87") + (and (eq_attr "vconstraint" "W84,W81,W82") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8")) (const_string "no") ] @@ -590,7 +587,7 @@ (eq_attr "fp_vector_disabled" "yes") (const_string "no") - (eq_attr "group_overlap_valid" "no") + (eq_attr "vconstraint_enabled" "no") (const_string "no") (eq_attr "spec_restriction_disabled" "yes") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 598aa8fba33..cb5174a5e91 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3747,7 +3747,7 @@ "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") (set_attr "mode" "") - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf4" @@ -3970,7 +3970,7 @@ (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])")) (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])")) (set (attr "avl_type_idx") (const_int 7)) - (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")]) + (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) ;; ------------------------------------------------------------------------------- ;; ---- Predicated integer Narrowing operations