From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 888CF385840D; Wed, 24 Apr 2024 02:46:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 888CF385840D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1713926818; bh=CG5wWRlsIbbJ2s+Fw0EslubCPrMCyKzc5E/yBoy3anY=; h=From:To:Subject:Date:From; b=nDxIMRkuUsd8jOMW0mase05WTrQMoip4qbuHjzzHFTNZlD5Gt0lVBg7QhBdTuQlFI ptaaPTm5Al4sd/1iX8c2nBZdVlXaa80NQBpAw68aFhA3hNnVuQzzxqE78D2PoBZOu2 ZOQYfC/2gif/Mo91+8rri0ozyJmIQ5g/6WaGSUz4= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-10102] Revert "RISC-V: Support highpart overlap for vext.vf" X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: 3091f1dfa7e8bf71f6012250d01b5a5ec85c2ca2 X-Git-Newrev: 8bcefc2d5fb0d8f8f9671fd830132b4e655c44b4 Message-Id: <20240424024658.888CF385840D@sourceware.org> Date: Wed, 24 Apr 2024 02:46:58 +0000 (GMT) List-Id: https://gcc.gnu.org/g:8bcefc2d5fb0d8f8f9671fd830132b4e655c44b4 commit r14-10102-g8bcefc2d5fb0d8f8f9671fd830132b4e655c44b4 Author: Pan Li Date: Wed Apr 24 10:46:28 2024 +0800 Revert "RISC-V: Support highpart overlap for vext.vf" This reverts commit 62685890d8861b72f812bfe171a20332df08bd49. Diff: --- gcc/config/riscv/vector.md | 19 ++-- .../gcc.target/riscv/rvv/base/pr112431-4.c | 104 --------------------- .../gcc.target/riscv/rvv/base/pr112431-5.c | 68 -------------- .../gcc.target/riscv/rvv/base/pr112431-6.c | 51 ---------- .../riscv/rvv/base/unop_v_constraint-2.c | 2 +- 5 files changed, 10 insertions(+), 234 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cb5174a5e91..6a4c0e6e10f 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -3730,24 +3730,23 @@ ;; Vector Double-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf2" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VWEXTI - (match_operand: 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))] + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" "vext.vf2\t%0,%3%p1" [(set_attr "type" "vext") - (set_attr "mode" "") - (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")]) + (set_attr "mode" "")]) ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf4" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c deleted file mode 100644 index 4cc6aa68b13..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-4.c +++ /dev/null @@ -1,104 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9, - size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14, - size_t sum15) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9 - + sum10 + sum11 + sum12 + sum13 + sum14 + sum15; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m2_t vw0 = __riscv_vsext_vf2_i16m2 (v0, vl); - vint16m2_t vw1 = __riscv_vsext_vf2_i16m2 (v1, vl); - vint16m2_t vw2 = __riscv_vsext_vf2_i16m2 (v2, vl); - vint16m2_t vw3 = __riscv_vsext_vf2_i16m2 (v3, vl); - vint16m2_t vw4 = __riscv_vsext_vf2_i16m2 (v4, vl); - vint16m2_t vw5 = __riscv_vsext_vf2_i16m2 (v5, vl); - vint16m2_t vw6 = __riscv_vsext_vf2_i16m2 (v6, vl); - vint16m2_t vw7 = __riscv_vsext_vf2_i16m2 (v7, vl); - vint16m2_t vw8 = __riscv_vsext_vf2_i16m2 (v8, vl); - vint16m2_t vw9 = __riscv_vsext_vf2_i16m2 (v9, vl); - vint16m2_t vw10 = __riscv_vsext_vf2_i16m2 (v10, vl); - vint16m2_t vw11 = __riscv_vsext_vf2_i16m2 (v11, vl); - vint16m2_t vw12 = __riscv_vsext_vf2_i16m2 (v12, vl); - vint16m2_t vw13 = __riscv_vsext_vf2_i16m2 (v13, vl); - vint16m2_t vw14 = __riscv_vsext_vf2_i16m2 (v14, vl); - vint16m2_t vw15 = __riscv_vsext_vf2_i16m2 (v15, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7); - size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8); - size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9); - size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10); - size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11); - size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12); - size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13); - size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14); - size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8, - sum9, sum10, sum11, sum12, sum13, sum14, sum15); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c deleted file mode 100644 index f7d668c624b..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-5.c +++ /dev/null @@ -1,68 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4, - size_t sum5, size_t sum6, size_t sum7) -{ - return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m2_t v0 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v1 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v2 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v3 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v4 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v5 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v6 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - vint8m2_t v7 = __riscv_vle8_v_i8m2 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m4_t vw0 = __riscv_vsext_vf2_i16m4 (v0, vl); - vint16m4_t vw1 = __riscv_vsext_vf2_i16m4 (v1, vl); - vint16m4_t vw2 = __riscv_vsext_vf2_i16m4 (v2, vl); - vint16m4_t vw3 = __riscv_vsext_vf2_i16m4 (v3, vl); - vint16m4_t vw4 = __riscv_vsext_vf2_i16m4 (v4, vl); - vint16m4_t vw5 = __riscv_vsext_vf2_i16m4 (v5, vl); - vint16m4_t vw6 = __riscv_vsext_vf2_i16m4 (v6, vl); - vint16m4_t vw7 = __riscv_vsext_vf2_i16m4 (v7, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m4_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m4_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m4_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m4_i16 (vw3); - size_t sum4 = __riscv_vmv_x_s_i16m4_i16 (vw4); - size_t sum5 = __riscv_vmv_x_s_i16m4_i16 (vw5); - size_t sum6 = __riscv_vmv_x_s_i16m4_i16 (vw6); - size_t sum7 = __riscv_vmv_x_s_i16m4_i16 (vw7); - - sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c deleted file mode 100644 index 3eed1198a70..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-6.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -size_t __attribute__ ((noinline)) -sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3) -{ - return sum0 + sum1 + sum2 + sum3; -} - -size_t -foo (char const *buf, size_t len) -{ - size_t sum = 0; - size_t vl = __riscv_vsetvlmax_e8m8 (); - size_t step = vl * 4; - const char *it = buf, *end = buf + len; - for (; it + step <= end;) - { - vint8m4_t v0 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v1 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v2 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - vint8m4_t v3 = __riscv_vle8_v_i8m4 ((void *) it, vl); - it += vl; - - asm volatile("nop" ::: "memory"); - vint16m8_t vw0 = __riscv_vsext_vf2_i16m8 (v0, vl); - vint16m8_t vw1 = __riscv_vsext_vf2_i16m8 (v1, vl); - vint16m8_t vw2 = __riscv_vsext_vf2_i16m8 (v2, vl); - vint16m8_t vw3 = __riscv_vsext_vf2_i16m8 (v3, vl); - - asm volatile("nop" ::: "memory"); - size_t sum0 = __riscv_vmv_x_s_i16m8_i16 (vw0); - size_t sum1 = __riscv_vmv_x_s_i16m8_i16 (vw1); - size_t sum2 = __riscv_vmv_x_s_i16m8_i16 (vw2); - size_t sum3 = __riscv_vmv_x_s_i16m8_i16 (vw3); - - sum += sumation (sum0, sum1, sum2, sum3); - } - return sum; -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c index f7a9e58292c..3344d423525 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c @@ -30,7 +30,7 @@ void f1 (void * in, void *out) ** vle16\.v\tv[0-9]+,0\([a-x0-9]+\) ** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ ** ... -** vsext\.vf2\tv[0-9]+,\s*v[0-9]+,\s*v0.t +** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t ** vse64\.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */