From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 5D84F38460B2; Thu, 25 Apr 2024 10:14:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5D84F38460B2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1714040080; bh=cmyz7rWydjgLh6EAw2WmMtlhselNyKDJb3pOcnKx6Kc=; h=From:To:Subject:Date:From; b=julpNlfMUwP98FTx6zwpx66bNfk0gd79+TadbOGSoHlKPRsXPUHAiWPwZPtElPw3G 7JDEAIlY3cLS42BTYiNA8uGbtWchXnIa6lOOAAmBR3Lbn4nYT0B4jCu16jgfRH63+2 Kbe85F2NCI3qjBhDeIDxmieNla9zbdwjMmyh7IQk= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-10118] RISC-V: Add test cases for insn does not satisfy its constraints [PR114714] X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: 10ad46bc191f8aa90b0d7b00963bfd52c6d7b09c X-Git-Newrev: af7d981ba40f145256f6f6d3409451e8fa647f75 Message-Id: <20240425101440.5D84F38460B2@sourceware.org> Date: Thu, 25 Apr 2024 10:14:40 +0000 (GMT) List-Id: https://gcc.gnu.org/g:af7d981ba40f145256f6f6d3409451e8fa647f75 commit r14-10118-gaf7d981ba40f145256f6f6d3409451e8fa647f75 Author: Pan Li Date: Thu Apr 25 15:04:02 2024 +0800 RISC-V: Add test cases for insn does not satisfy its constraints [PR114714] We have one ICE when RVV register overlap is enabled. We reverted this feature as it is in stage 4 and there is no much time to figure a better solution for this. Thus, for now add the related test cases which will trigger ICE when register overlap enabled. This will gate the RVV register overlap support in GCC-15. PR target/114714 gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr114714-1.C: New test. * g++.target/riscv/rvv/base/pr114714-2.C: New test. Signed-off-by: Pan Li Co-Authored-by: Kito Cheng Diff: --- .../g++.target/riscv/rvv/base/pr114714-1.C | 85 ++++++++++++++++++++++ .../g++.target/riscv/rvv/base/pr114714-2.C | 85 ++++++++++++++++++++++ 2 files changed, 170 insertions(+) diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C new file mode 100644 index 00000000000..d3230f7f23e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-1.C @@ -0,0 +1,85 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */ + +typedef int a; +typedef short b; +typedef unsigned c; +template < typename > using e = unsigned; +template < typename > void ab(); +#pragma riscv intrinsic "vector" +template < typename f, int, int ac > struct g { + using i = f; + template < typename m > using j = g< m, 0, ac >; + using k = g< i, 1, ac - 1 >; + using ad = g< i, 1, ac + 1 >; +}; +namespace ae { +struct af { + using h = g< short, 6, 0 < 3 >; +}; +struct ag { + using h = af::h; +}; +} template < typename, int > using ah = ae::ag::h; +template < class ai > using aj = typename ai::i; +template < class i, class ai > using j = typename ai::j< i >; +template < class ai > using ak = j< e< ai >, ai >; +template < class ai > using k = typename ai::k; +template < class ai > using ad = typename ai::ad; +template < a ap > vuint16m1_t ar(g< b, ap, 0 >, b); +template < a ap > vuint16m2_t ar(g< b, ap, 1 >, b); +template < a ap > vuint32m2_t ar(g< c, ap, 1 >, c); +template < a ap > vuint32m4_t ar(g< c, ap, 2 >, c); +template < class ai > using as = decltype(ar(ai(), aj< ai >())); +template < class ai > as< ai > at(ai); +namespace ae { +template < int ap > vuint32m4_t au(g< c, ap, 1 + 1 >, vuint32m2_t l) { + return __riscv_vlmul_ext_v_u32m2_u32m4(l); +} +} template < int ap > vuint32m2_t aw(g< c, ap, 1 >, vuint16m1_t l) { + return __riscv_vzext_vf2_u32m2(l, 0); +} +namespace ae { +vuint32m4_t ax(vuint32m4_t, vuint32m4_t, a); +} +template < class ay, class an > as< ay > az(ay ba, an bc) { + an bb; + return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2); +} +template < class bd > as< bd > be(bd, as< ad< bd > >); +namespace ae { +template < class bh, class bi > void bj(bh bk, bi bl) { + ad< decltype(bk) > bn; + az(bn, bl); +} +} template < int ap, int ac, class bp, class bq > +void br(g< c, ap, ac > bk, bp, bq bl) { + ae::bj(bk, bl); +} +template < class ai > using bs = decltype(at(ai())); +struct bt; +template < int ac = 1 > class bu { +public: + template < typename i > void operator()(i) { + ah< i, ac > d; + bt()(i(), d); + } +}; +struct bt { + template < typename bv, class bf > void operator()(bv, bf bw) { + using bx = bv; + ak< bf > by; + k< bf > bz; + using bq = bs< decltype(by) >; + using bp = bs< decltype(bw) >; + bp cb; + ab< bx >(); + for (;;) { + bp cc; + bq bl = aw(by, be(bz, cc)); + br(by, cb, bl); + } + } +}; +void d() { bu()(b()); } diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C new file mode 100644 index 00000000000..55621e98fee --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr114714-2.C @@ -0,0 +1,85 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -std=c++17" } */ + +typedef int a; +typedef short b; +typedef unsigned c; +template < typename > using e = unsigned; +template < typename > void ab(); +#pragma riscv intrinsic "vector" +template < typename f, int, int ac > struct g { + using i = f; + template < typename m > using j = g< m, 0, ac >; + using k = g< i, 1, ac - 1 >; + using ad = g< i, 1, ac + 1 >; +}; +namespace ae { +struct af { + using h = g< short, 6, 0 < 3 >; +}; +struct ag { + using h = af::h; +}; +} template < typename, int > using ah = ae::ag::h; +template < class ai > using aj = typename ai::i; +template < class i, class ai > using j = typename ai::j< i >; +template < class ai > using ak = j< e< ai >, ai >; +template < class ai > using k = typename ai::k; +template < class ai > using ad = typename ai::ad; +template < a ap > vuint16mf2_t ar(g< b, ap, 0 >, b); +template < a ap > vuint16m1_t ar(g< b, ap, 1 >, b); +template < a ap > vuint32m1_t ar(g< c, ap, 1 >, c); +template < a ap > vuint32m2_t ar(g< c, ap, 2 >, c); +template < class ai > using as = decltype(ar(ai(), aj< ai >())); +template < class ai > as< ai > at(ai); +namespace ae { +template < int ap > vuint32m2_t au(g< c, ap, 1 + 1 >, vuint32m1_t l) { + return __riscv_vlmul_ext_v_u32m1_u32m2(l); +} +} template < int ap > vuint32m1_t aw(g< c, ap, 1 >, vuint16mf2_t l) { + return __riscv_vzext_vf2_u32m1(l, 0); +} +namespace ae { +vuint32m2_t ax(vuint32m2_t, vuint32m2_t, a); +} +template < class ay, class an > as< ay > az(ay ba, an bc) { + an bb; + return ae::ax(ae::au(ba, bc), ae::au(ba, bb), 2); +} +template < class bd > as< bd > be(bd, as< ad< bd > >); +namespace ae { +template < class bh, class bi > void bj(bh bk, bi bl) { + ad< decltype(bk) > bn; + az(bn, bl); +} +} template < int ap, int ac, class bp, class bq > +void br(g< c, ap, ac > bk, bp, bq bl) { + ae::bj(bk, bl); +} +template < class ai > using bs = decltype(at(ai())); +struct bt; +template < int ac = 1 > class bu { +public: + template < typename i > void operator()(i) { + ah< i, ac > d; + bt()(i(), d); + } +}; +struct bt { + template < typename bv, class bf > void operator()(bv, bf bw) { + using bx = bv; + ak< bf > by; + k< bf > bz; + using bq = bs< decltype(by) >; + using bp = bs< decltype(bw) >; + bp cb; + ab< bx >(); + for (;;) { + bp cc; + bq bl = aw(by, be(bz, cc)); + br(by, cb, bl); + } + } +}; +void d() { bu()(b()); }