From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 4088F3858D20; Fri, 26 Apr 2024 00:25:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4088F3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1714091120; bh=jEQWfqjNe45hN7BIPUf4mQtcYuJKGr4f5ee+IqSxZwQ=; h=From:To:Subject:Date:From; b=ihQqOEZFk80h4JDiapzD0mWHWLlkS7gsC17hiq1zDGXH7IW6izG2c2baT/Dpz8AVA oYMUU2VvYxuXU5Z0F8qlZL1elYqp0FtZ8net7NutwroccWlctuzDcoHxKD2UcaagaL pxxI7yCCc76OwcR8wAkRW9xN39xY2gK9Xv0yfZfU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work164-test)] Add -mmfspr option. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work164-test X-Git-Oldrev: eebc665799dc3cacf8c57f62863b489e07d6066d X-Git-Newrev: cdcfeb5aa467d17024891bdbc218531151b0f1d6 Message-Id: <20240426002520.4088F3858D20@sourceware.org> Date: Fri, 26 Apr 2024 00:25:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:cdcfeb5aa467d17024891bdbc218531151b0f1d6 commit cdcfeb5aa467d17024891bdbc218531151b0f1d6 Author: Michael Meissner Date: Thu Apr 25 20:24:59 2024 -0400 Add -mmfspr option. 2024-04-25 Michael Meissner gcc/ * config/rs6000/rs6000-cpus.def (ISA_MASKS_2_7_SERVER): Add -mmfspr. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.cc (rs6000_register_move_cost): Check -mmfspr. * config/rs6000/rs6000.opt (-mmfspr): New option. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 2 ++ gcc/config/rs6000/rs6000.cc | 3 ++- gcc/config/rs6000/rs6000.opt | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 7ea3ce09c8d..ecb9471d84a 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -51,6 +51,7 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ + | OPTION_MASK_MFSPR \ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC \ | OPTION_MASK_TAR) @@ -138,6 +139,7 @@ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ + | OPTION_MASK_MFSPR \ | OPTION_MASK_MMA \ | OPTION_MASK_MODULO \ | OPTION_MASK_MULHW \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e5ebbd58cc0..4df4259335b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -22816,7 +22816,8 @@ rs6000_register_move_cost (machine_mode mode, /* Make moves from SPR registers (LR, CTR, TAR) more expensive so that the register allocator does not think of these registers are useful for saving results. */ - else if (reg_classes_intersect_p (from, SPECIAL_REGS) + else if (TARGET_MFSPR + && reg_classes_intersect_p (from, SPECIAL_REGS) && reg_classes_intersect_p (to, GENERAL_REGS)) { rclass = from; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 8e9215a32c2..2cbf7c1db1c 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -607,6 +607,10 @@ mtar Target Mask(TAR) Var(rs6000_isa_flags) Generate (do not generate) code using the TAR register. +mmfspr +Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags) +Generate (do not generate) code making move from SPR register expensive. + mrelative-jumptables Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save