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From: Alexandre Oliva <aoliva@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
Date: Sun, 28 Apr 2024 05:21:38 +0000 (GMT)	[thread overview]
Message-ID: <20240428052138.1B1533858C52@sourceware.org> (raw)

https://gcc.gnu.org/g:7d9771291b4943de287cadd09d94a80512158376

commit 7d9771291b4943de287cadd09d94a80512158376
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Sun Apr 21 17:24:21 2024 -0300

    decay vect tests from run to link for pr95401
    
    When vect.exp finds our configuration disables altivec by default, it
    disables the execution of vectorization tests, assuming the test
    hardware doesn't support it.
    
    Tests become just compile tests, but compile tests won't work
    correctly when additional sources are named, e.g. pr95401.cc, because
    GCC refuses to compile multiple files into the same asm output.
    
    With this patch, the default for when execution is not possible
    becomes link.
    
    
    for  gcc/testsuite/ChangeLog
    
            * lib/target-supports.exp (check_vect_support_and_set_flags):
            Decay to link rather than compile.

Diff:
---
 gcc/testsuite/lib/target-supports.exp | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
         if [check_750cl_hw_available] {
             set dg-do-what-default run
         } else {
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif [istarget powerpc*-*-*] {
         # Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
                 # some other cpu type specified above.
 		set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0 "-mcpu=970"]
             }
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
         lappend DEFAULT_VECTCFLAGS "-msse2"
         if { [check_effective_target_sse2_runtime] } {
             set dg-do-what-default run
         } else {
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif { [istarget mips*-*-*]
 	       && [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
         if [check_effective_target_ultrasparc_hw] {
             set dg-do-what-default run
         } else {
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif [istarget alpha*-*-*] {
         # Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
         if [check_alpha_max_hw_available] {
             set dg-do-what-default run
         } else {
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif [istarget ia64-*-*] {
         set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
         if [is-effective-target arm_neon_hw] {
             set dg-do-what-default run
         } else {
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif [istarget aarch64*-*-*] {
         set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
             set dg-do-what-default run
         } else {
 	    lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-            set dg-do-what-default compile
+            set dg-do-what-default link
         }
     } elseif [istarget amdgcn-*-*] {
         set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
 	    foreach item [add_options_for_riscv_v ""] {
 		lappend DEFAULT_VECTCFLAGS $item
 	    }
-	    set dg-do-what-default compile
+	    set dg-do-what-default link
 	}
     } elseif [istarget loongarch*-*-*] {
       # Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
       if [check_effective_target_loongarch_sx_hw] {
 	  set dg-do-what-default run
       } else {
-	  set dg-do-what-default compile
+	  set dg-do-what-default link
       }
     } else {
         return 0

             reply	other threads:[~2024-04-28  5:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-28  5:21 Alexandre Oliva [this message]
  -- strict thread matches above, loose matches on Subject: below --
2024-04-23  2:38 Alexandre Oliva
2024-04-22  6:57 Alexandre Oliva
2024-04-22  5:13 Alexandre Oliva
2024-04-21 20:27 Alexandre Oliva
2023-04-06  6:34 Alexandre Oliva
2023-03-30 14:07 Alexandre Oliva
2023-03-24  6:24 Alexandre Oliva
2023-03-23  3:47 Alexandre Oliva
2023-03-16 14:22 Alexandre Oliva
2023-03-15 14:05 Alexandre Oliva
2021-03-11 10:21 Alexandre Oliva

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