[gcc r15-647] RISC-V: Implement -m{,no}fence-tso

[Jeff Law <law@gcc.gnu.org>]

https://gcc.gnu.org/g:a6114c2a691112f9cf5b072c21685d2e43c76d81

commit r15-647-ga6114c2a691112f9cf5b072c21685d2e43c76d81
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date:   Sat May 18 15:15:09 2024 -0600

    RISC-V: Implement -m{,no}fence-tso
    
    Some processors from T-Head don't implement the `fence.tso` instruction
    natively and instead trap to firmware.  This breaks some users who
    haven't yet updated the firmware and one could imagine it breaking users
    who are trying to build firmware if they're using the C memory model.
    
    So just add an option to disable emitting it, in a similar fashion to
    how we allow users to forbid other instructions.
    
    Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1070959
    ---
    I've just smoke tested this one, but
    
        void func(void) { __atomic_thread_fence(__ATOMIC_ACQ_REL); }
    
    generates `fence.tso` without the argument and `fence rw,rw` with
    `-mno-fence-tso`, so it seems to be at least mostly there.  I figured
    I'd just send it up for comments before putting together the DG bits:
    it's kind of a pain to carry around these workarounds for unimplemented
    instructions, but it's in HW so there's not much we can do about that.
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.opt: Add -mno-fence-tso.
            * config/riscv/sync-rvwmo.md (mem_thread_fence_rvwmo): Respect
            -mno-fence-tso.
            * doc/invoke.texi (RISC-V): Document -mno-fence-tso.

Diff:
---
 gcc/config/riscv/riscv.opt     | 4 ++++
 gcc/config/riscv/sync-rvwmo.md | 2 +-
 gcc/doc/invoke.texi            | 8 ++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index d209ac896fde..87f583320168 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -624,3 +624,7 @@ Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)
 mtls-dialect=
 Target RejectNegative Joined Enum(tls_type) Var(riscv_tls_dialect) Init(TLS_TRADITIONAL) Save
 Specify TLS dialect.
+
+mfence-tso
+Target Var(TARGET_FENCE_TSO) Init(1)
+Specifies whether the fence.tso instruction should be used.
diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index d4fd26069f74..e639a1e23924 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -33,7 +33,7 @@
     if (model == MEMMODEL_SEQ_CST)
 	return "fence\trw,rw";
     else if (model == MEMMODEL_ACQ_REL)
-	return "fence.tso";
+	return TARGET_FENCE_TSO ? "fence.tso" : "fence\trw,rw";
     else if (model == MEMMODEL_ACQUIRE)
 	return "fence\tr,rw";
     else if (model == MEMMODEL_RELEASE)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b9408ecc9188..70e8004a71b2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1244,6 +1244,7 @@ See RS/6000 and PowerPC Options.
 -mplt  -mno-plt
 -mabi=@var{ABI-string}
 -mfdiv  -mno-fdiv
+-mfence-tso  -mno-fence-tso
 -mdiv  -mno-div
 -misa-spec=@var{ISA-spec-string}
 -march=@var{ISA-string}
@@ -30436,6 +30437,13 @@ Do or don't use hardware floating-point divide and square root instructions.
 This requires the F or D extensions for floating-point registers.  The default
 is to use them if the specified architecture has these instructions.
 
+@opindex mfence-tso
+@item -mfence-tso
+@itemx -mno-fence-tso
+Do or don't use the @samp{fence.tso} instruction, which is unimplemented on
+some processors (including those from T-Head).  If the @samp{fence.tso}
+instruction is not availiable then a stronger fence will be used instead.
+
 @opindex mdiv
 @item -mdiv
 @itemx -mno-div