Re: -msse producing sse2 instructions

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

I found a cool util wcpuid and ran it, and found to my great surprise that
the SSE function was disabled.

The motherboard and bios are brand new as of last week (and fully updated)
so its very strange that they wouldn't have enabled the SSE feature set.  I
couldn't find anything in the BIOS configuration screen that looked like
"Enable SSE".

So you are right, it isn't a gcc problem, sorry for the bother.  Now I've
just got to work out how the hell I can switch on the SSE feature.

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com

----- Original Message -----
From: "Andreas Jaeger" <aj@suse.de>
To: "Dylan Cuthbert" <dylan@q-games.com>
Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>; <tprince@computer.org>
Sent: Monday, July 22, 2002 2:41 PM
Subject: Re: -msse producing sse2 instructions


> "Dylan Cuthbert" <dylan@q-games.com> writes:
>
> > Hi all,
> >
> > I managed to whittle it down to the place where the instruction is being
> > generated.. and the resulting executable produces an Illegal Instruction
if
> > run on Athlon 4 machines, but not on Athlon MP/XP or Pentium 4s.
> >
> > The line to compile with:
> >
> > $>
> >
g++ -mcpu=pentium3 -march=pentium3 -msse -mfpmath=387 -mpreferred-stack-boun
> >
dary=4 -fno-implement-inlines -Werror -Wall  -Dstdext=__gnu_cxx -O2 -mno-cyg
> > win -mwin32  test.cpp -o test.exe
> >
> > Compiling with -march=athlon-4 -mcpu=athlon-4 also causes the same code
to
> > be generated.
> >
> > On another note, I also get an illegal instruction error on this:
> >
> > movss  0xfffffffc(%ebp),%xmm0
> >
> > Seems to be in the integer->float conversion code tho. so I hope this
helps.
>
> I compiled your code and it worked fine on both my Pentium III and
> Athlon MP.
>
> The first Athlon4 systems had SSE disabled in the BIOS.  As Honza
> already mentioned, you should use the cpuid instruction and check
> whether your systems support SSE at all.
>
> For example my Athlon4 reports these flags via cpuinfo (this is read
> from a Linux file):
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 mmx fxsr sse syscall mmxext 3dnowext 3dnow
>
> Please write some assembler and check whether the Athlons do support
> SSE and if not, investigate why not.
>
> I do not think that this is a GCC problem,
> Andreas
> --
>  Andreas Jaeger
>   SuSE Labs aj@suse.de
>    private aj@arthur.inka.de
>     http://www.suse.de/~aj