Questions about gcc under em64t architecture

Questions about gcc under em64t architecture

[Mark Cuss]

Hello list!

I've got some questions regarding compiling code under the em64t 
architecture...  I've never dealt with 64 bit stuff before so please bear 
with me...

First of all - the machine in question:  I got this new server to act as a 
compile machine on our network:
IBM eServer x366:
- Four Xeon 3.66 GHz CPUs (with HT turned on, so /proc/cpuinfo shows 8 
CPUs).  One of the listings from cpuinfo is included below...
- 8 GB RAM
- RHEL AS v4

The compiler that ships with the machine (gcc 3.4.3) will build 32 bit code 
when I pass in the -m32 option, so that is a good first step.

On my current server (Dual Xeon @ 2.2 GHz) I have gcc 3.3.3 built and 
working.  I was hoping I could just call this compiler on my em64t machine - 
I know that the new platform will run 32 bit code, but this doesn't seem to 
work well - it calls the 32 bit compiler, but the 64 bit native assembler 
and linker and causes grief...  Also, the 32 bit version of gcc seems to run 
really slow on the 64 bit box - it takes it a few seconds just to return the 
output from gcc -v, while the 64 bit version returns instantly.

So - my question for the list is:  Does anyone know how I can set up my new 
toy to build 32 bit code?  I tried to build gcc 3.4.4 on the machine with 
the target set to i686-pc-linux-gnu, but it wouldn't build.  If anyone has 
any insight into setting up an environment where I can build 32 bit 
executables  on an em64t box I'd really appreciate the advice.

Thanks in advance,

Mark

cpuinfo:

processor       : 7
vendor_id       : GenuineIntel
cpu family      : 15
model           : 4
model name      :                Intel(R) Xeon(TM) MP CPU 3.66GHz
stepping        : 1
cpu MHz         : 3670.048
cache size      : 1024 KB
physical id     : 11
siblings        : 2
fpu             : yes
fpu_exception   : yes
cpuid level     : 5
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca 
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni 
monitor ds_cpl est tm2 cid cx16 xtpr
bogomips        : 7323.64
clflush size    : 64
cache_alignment : 128
address sizes   : 40 bits physical, 48 bits virtual
power management:



Mark Cuss, B. Sc.
Real Time Systems Analyst
System Administrator
CDL Systems Ltd
Suite 230
3553 - 31 Street NW
Calgary, AB, Canada

Phone: 403 289 1733 ext 226
Fax: 403 289 3967
www.cdlsystems.com