From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from asav21.altibox.net (asav21.altibox.net [109.247.116.8]) by sourceware.org (Postfix) with ESMTPS id 375303857C4E for ; Sun, 11 Oct 2020 12:51:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 375303857C4E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=hesbynett.no Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=david.brown@hesbynett.no Received: from mail.jansenbrown.no (unknown [92.221.34.247]) by asav21.altibox.net (Postfix) with ESMTP id D739F800EF; Sun, 11 Oct 2020 14:51:44 +0200 (CEST) Received: from [192.168.4.245] (unicorn.lan [192.168.4.245]) by mail.jansenbrown.no (Postfix) with ESMTPSA id 819E0201182; Sun, 11 Oct 2020 14:51:44 +0200 (CEST) Subject: Re: Atomic accesses on ARM microcontrollers To: Toby Douglass References: <945d5e74-b449-3746-6560-996d0437db76@hesbynett.no> <015e0ad8-8052-c63f-0eb1-4b9fa817cc10@hesbynett.no> <08ef1c04-8e03-5ae8-e070-0499984f21bd@hesbynett.no> <24c49c76-43c3-9a0d-6b02-a4340b1fccba@winterflaw.net> Cc: GCC help From: David Brown Openpgp: preference=signencrypt Autocrypt: addr=david.brown@hesbynett.no; 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Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <24c49c76-43c3-9a0d-6b02-a4340b1fccba@winterflaw.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 8bit X-CMAE-Score: 0 X-CMAE-Analysis: v=2.3 cv=VKvzYeHX c=1 sm=1 tr=0 a=+Fy6h7hJ4UJcWgHwdIx3jg==:117 a=+Fy6h7hJ4UJcWgHwdIx3jg==:17 a=IkcTkHD0fZMA:10 a=afefHYAZSVUA:10 a=_hl0f72EX2yYNIlrCBUA:9 a=QEXdDO2ut3YA:10 X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, NICE_REPLY_A, SPF_HELO_NONE, SPF_NEUTRAL, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 11 Oct 2020 12:51:47 -0000 On 11/10/2020 14:34, Toby Douglass wrote: > On 11/10/2020 14:16, David Brown wrote: > >>> I could be wrong, but I think the only way you can do this with atomics >>> is copy-on-write.  Make a new copy of the data, and use an atomic to >>> flip a pointer, so the readers move atomically from the old version to >>> the new version. >> >> I've been thinking a bit more about this, inspired by your post here. >> And I believe you are correct - neither ldrex/strex nor load/store >> double register is sufficient for 64-bit atomic accesses on the 32-bit >> ARM, even for plain reads and writes. > > No - I think you can have 64-bit atomic stores on a 32-bit CPU.  There > *is* a double word atomic compare-and-swap. Certainly it is possible - if the cpu has such an instruction. The Cortex-M cores do not. >  If you define a 64-bit > integer type, and use it with __atomic_compare_exchange_n(), you should > get a 64-bit atomic swap.  In older versions of the library, I actually > had inline assembly for this, but I realised in the end I could in fact > get GCC to emit the correct code. > > However, I don't understand how a double-word atomic store helps you.  > If you have an arbitrarily-sized block of memory to update atomically, > how can you use a 64-bit atomic store to do this? > It would not help for arbitrary blocks of memory, but it /would/ help for 64-bit blocks. And that would cover a sizeable majority of use-cases for me. >> One thing we can all be sure about - this stuff is difficult, it needs a >> /lot/ of thought, and the documentation is often poor on the critical >> details. > > Amen. >