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From: =?utf-8?B?UGF3ZcWC?= Sikora <pluto@agmk.net>
To: gcc-help@gcc.gnu.org, its.dipanjan.das@gmail.com
Cc: Gert Hulselmans <hulselmansgert@gmail.com>
Subject: Re: Bit field ordering on Big-Endian (SPARC) processor
Date: Tue, 11 Dec 2012 17:04:00 -0000
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On Tuesday 11 of December 2012 18:31:06 Dipanjan Das wrote:
> Consider the code below:
>=20
> #define FORCE_CAST(var, type) *(type*)&var

^^^^^^^^^^^^^^^^ don't forget to use -fno-strict-aliasing with such ugly tr=
icks.

> struct processor_status_register
> {
> unsigned int cwp:5;
> unsigned int et:1;
> unsigned int ps:1;
> unsigned int s:1;
> unsigned int pil:4;
> unsigned int ef:1;
> unsigned int ec:1;
> unsigned int reserved:6;
>=20
> unsigned int c:1;
> unsigned int v:1;
> unsigned int z:1;
> unsigned int n:1;
>=20
> unsigned int ver:4;
> unsigned int impl:4;
> }__attribute__ ((__packed__));

iirc, the C language gives no guarantee of the ordering of fields within ma=
chine words,
so if you use them for the h/w register modeling, you program will not only=
 be nonportable,
it will be compiler-dependent too. you should really read suitable byte/wor=
d/doubleword
from mapped h/w memory, convert it with le/be_to_cpu() method and shift/mas=
k to access bits.

BR,
Pawe=C5=82.