Re: Does a target system must support indexing?

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From: "Setjem Setjem" <Setjem@gmx.de>
To: Ian Lance Taylor <iant@google.com>
Cc: gcc-help@gcc.gnu.org
Subject: Re: Does a target system must support indexing?
Date: Mon, 04 Jun 2012 07:37:00 -0000	[thread overview]
Message-ID: <20120604073636.220760@gmx.net> (raw)

[-- Attachment #1: Type: text/plain, Size: 3545 bytes --]

-------- Original-Nachricht --------
> Datum: Fri, 01 Jun 2012 07:55:33 -0700
> Von: Ian Lance Taylor <iant@google.com>
> An: "Setjem Setjem" <Setjem@gmx.de>
> CC: Georg-Johann Lay <avr@gjlay.de>, gcc-help@gcc.gnu.org
> Betreff: Re: Does a target system must support indexing?

> "Setjem Setjem" <Setjem@gmx.de> writes:
> 
> >> Look at TARGET_LEGITIMIZE_ADDRESS and at expand time you can
> >> force the [reg+const] addresses into a register.
> >
> > Thank you very much,
> >
> > Let me get this right that expand time is the time before reload is in
> progress? 
> >
> > Now i have implemeted TARGET_LEGITIMIZE_ADDRESS:
> 
> But have you done the "at expand time" part?  That means that you need
> to write movMODE as a define_expand that stuffs the address into a
> register.
> 
> Ian

Hi Ian,
thanks for your answer. Sorry that i didn't reply over the weekend but i had no time. I added some instructions within the define_expand move<mode> and now it looks like this:

(define_expand "mov<mode>"
   [(set (match_operand:QISI 0 "nonimmediate_operand"   "")
         (match_operand:QISI 1 "general_operand"    ""))]
   ""
   "
   {   
      fprintf(stderr, \"mov %s:\n\", GET_MODE_NAME(<MODE>mode));
      debug_rtx(operands[0]);
      debug_rtx(operands[1]);
		
      /*  One of the ops has to be in a register */
      if  (      ! register_operand(operands[0], <MODE>mode)
            &&  !(register_operand(operands[1], <MODE>mode)))
      {
         operands[1] = copy_to_mode_reg(<MODE>mode, operands[1]);
      }    

      /*  Do not allow side effects for operand 0 in addresses */
      if( MEM_P(operands[0]) )
      {
         rtx adr = (XEXP (operands[0],0));
         if (GET_CODE (adr) == PLUS && REG_P (XEXP (adr,0)) )
         {
            if (REG_P (XEXP (adr,1)) || (GET_CODE (XEXP (adr, 1)) == CONST_INT))
            {
               emit_insn(gen_addsi3(XEXP (adr,0), XEXP (adr,0), XEXP (adr,1)));
               operands[0] = gen_rtx_MEM(<MODE>mode,XEXP (adr,0));
               fprintf(stderr, \"after:\n\");
               debug_rtx(operands[0]);
               debug_rtx(operands[1]);
            }
         }   
      }
      
      /*  Do not allow side effects for operand 1 in addresses */
      if( MEM_P(operands[1]) )
      {
         rtx adr = (XEXP (operands[1],0));
         if (GET_CODE (adr) == PLUS && REG_P (XEXP (adr,0)) )
         {
            if (REG_P (XEXP (adr,1)) || (GET_CODE (XEXP (adr, 1)) == CONST_INT))
            {
               emit_insn(gen_addsi3(XEXP (adr,0), XEXP (adr,0), XEXP (adr,1)));
               operands[1] = gen_rtx_MEM(<MODE>mode,XEXP (adr,0));
               fprintf(stderr, \"after:\n\");
               debug_rtx(operands[0]);
               debug_rtx(operands[1]);
            }
         }   
      }
   fprintf(stderr, \"\n\");
   }"
)

(define_insn "*mov<mode>"
   [(set   (match_operand:QISI 0 "nonimmediate_operand"   "")
         (match_operand:QISI 1 "general_operand"    ""))]
   "      register_operand(operands[0], <MODE>mode)
      ||  register_operand(operands[1], <MODE>mode)"
   "* return menmic_mov_out(operands[0], operands[1], <MODE>mode);"
   [(set_attr "length" "1")]
)

But the problem is still the same. I don't get it. Why the compiler pass an address with side effect after the reload is completed and where? The compiled fail.c is the same as before. I attached the new debug log and hope you could help me.

-- 
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[-- Attachment #2: debug.txt --]
[-- Type: text/plain, Size: 32464 bytes --]

menmic_option_override
menmic_asm_init_sections
menmic_legitimate_address_p
mode: (QI)    : 
address: 
(mem:SI (plus:SI (reg:SI 38)
        (const_int 4 [0x4])) [0 S4 A32])
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(mem:SI (symbol_ref:SI ("foo")) [0 S4 A32])
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 0 r0))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 1 r1))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 2 r2))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 3 r3))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 4 r4))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 5 r5))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 6 r6))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 7 r7))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 8 r8))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 9 r9))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 10 r10))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 11 r11))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 12 r12))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 13 r13))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 14 r14))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 15 r15))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 16 r16))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 17 r17))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 18 r18))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 19 r19))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 20 r20))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 21 r21))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 22 r22))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 23 r23))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 24 r24))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 25 r25))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 26 r26))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 27 r27))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 28 r28))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 29 r29))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 30 r30))
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (QI)    : 
address: 
(plus:SI (plus:SI (reg:SI 18 r18)
        (reg:SI 31 r31))
    (const_int 4 [0x4]))
ret_val false 

menmic_init_machine_status
menmic_init_machine_status
menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 29 r29)
menmic_regno_ok_for_base_p: return: 29
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 29 r29)
menmic_regno_ok_for_base_p: return: 29
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 34 virtual-stack-dynamic)
ret_val true 

mov SI:
(reg:SI 32 virtual-incoming-args)
(reg:SI 33 virtual-stack-vars)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 34 virtual-stack-dynamic)
ret_val true 

mov SI:
(mem:SI (reg:SI 34 virtual-stack-dynamic) [0 S4 A32])
(reg:SI 32 virtual-incoming-args)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 34 virtual-stack-dynamic)
ret_val true 

mov SI:
(reg:SI 33 virtual-stack-vars)
(mem:SI (reg:SI 34 virtual-stack-dynamic) [0 S4 A32])

mov SI:
(reg:SI 32 virtual-incoming-args)
(reg:SI 33 virtual-stack-vars)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 34 virtual-stack-dynamic)
ret_val true 

mov SI:
(mem:SI (reg:SI 34 virtual-stack-dynamic) [0 S4 A32])
(reg:SI 32 virtual-incoming-args)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 34 virtual-stack-dynamic)
ret_val true 

mov SI:
(reg:SI 33 virtual-stack-vars)
(mem:SI (reg:SI 34 virtual-stack-dynamic) [0 S4 A32])

 failmenmic_init_machine_status

Analyzing compilation unit
menmic_init_cumulative_args
menmic_num_arg_regs regnums: 1
menmic_function_arg_advance:
nregs: 3
regno: 21
Performing interprocedural optimizations
 <*free_lang_data> <visibility> <early_local_cleanups> <emutls> <whole-program> <inline>Assembling functions:
 failmov SI:
(reg:SI 40)
(reg/f:SI 32 virtual-incoming-args)

menmic_init_cumulative_args
menmic_num_arg_regs regnums: 1
menmic_function_arg
menmic_num_arg_regs regnums: 1
menmic_function_arg_advance:
nregs: 3
regno: 21
menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

mov SI:
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
(reg:SI 20 r20 [ v ])

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false 

legitimize_address:
old: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
new: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

mov SI:
(reg:SI 41)
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (DI)    : 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (DI)    : 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (DI)    : 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 41)
ret_val true 

mov SI:
(subreg:SI (reg:DI 38 [ D.1920 ]) 0)
(mem:SI (reg/f:SI 41) [0 *v_1(D)+0 S4 A64])

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(plus:SI (reg/f:SI 41)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(plus:SI (reg/f:SI 41)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(plus:SI (reg/f:SI 41)
    (const_int 4 [0x4]))
ret_val false 

legitimize_address:
old: mode: SI
(plus:SI (reg/f:SI 41)
    (const_int 4 [0x4]))
new: mode: SI
(reg:SI 42)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 42)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 42)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 42)
ret_val true 

mov SI:
(subreg:SI (reg:DI 38 [ D.1920 ]) 4)
(mem:SI (reg/f:SI 42) [0 *v_1(D)+4 S4 A32])

mov SI:
(subreg:SI (reg:DI 43) 0)
(const_int 1 [0x1])

mov SI:
(subreg:SI (reg:DI 43) 4)
(const_int 0 [0])

mov SI:
(reg:SI 45)
(const_int 1 [0x1])

mov SI:
(reg:SI 45)
(const_int 0 [0])

mov SI:
(subreg:SI (reg:DI 44) 4)
(reg:SI 46)

mov SI:
(subreg:SI (reg:DI 39 [ D.1921 ]) 0)
(subreg:SI (reg:DI 44) 0)

mov SI:
(subreg:SI (reg:DI 39 [ D.1921 ]) 4)
(subreg:SI (reg:DI 44) 4)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
ret_val false 

legitimize_address:
old: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])
new: mode: SI
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

mov SI:
(reg:SI 47)
(mem/f/c/i:SI (reg/f:SI 33 virtual-stack-vars) [0 v+0 S4 A32])

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (DI)    : 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (DI)    : 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (DI)    : 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 47)
ret_val true 

mov SI:
(mem:SI (reg/f:SI 47) [0 *v_1(D)+0 S4 A64])
(subreg:SI (reg:DI 39 [ D.1921 ]) 0)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(plus:SI (reg/f:SI 47)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(plus:SI (reg/f:SI 47)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(plus:SI (reg/f:SI 47)
    (const_int 4 [0x4]))
ret_val false 

legitimize_address:
old: mode: SI
(plus:SI (reg/f:SI 47)
    (const_int 4 [0x4]))
new: mode: SI
(reg:SI 48)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 48)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg:SI 48)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 48)
ret_val true 

mov SI:
(mem:SI (reg/f:SI 48) [0 *v_1(D)+4 S4 A32])
(subreg:SI (reg:DI 39 [ D.1921 ]) 4)

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 42)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 33 virtual-stack-vars)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    : 
address: 
(reg/f:SI 48)
ret_val true 

menmic_incoming_return_addr_rtx
menmic_incoming_return_addr_rtx
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 16 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 16 
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 41)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 42)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 42)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 18 r18)
menmic_regno_ok_for_base_p: return: 18
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 47)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 48)
ret_val true 

menmic_legitimate_address_p
mode: (SI)    (reg_renumber): 
address: 
(reg/f:SI 48)
ret_val true 

menmic_can_eliminate
menmic_can_eliminate
menmic_can_eliminate
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52 
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 12 [0xc]))
ret_val false 

menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 20 [0x14]))
ret_val false 

menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 20 [0x14]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 20 [0x14]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 32 [0x20]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 32 [0x20]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 8 [0x8]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 8 [0x8]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 24 [0x18]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 24 [0x18]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 32 [0x20]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 32 [0x20]))
ret_val false 

menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 52 
menmic_initial_elimination_offset
menmic_can_eliminate
menmic_can_eliminate
menmic_frame_pointer_required_p
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 12 [0xc]))
ret_val false 

menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 20 [0x14]))
ret_val false 

menmic_legitimate_address_p
mode: (DI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 20 [0x14]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 20 [0x14]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 32 [0x20]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 32 [0x20]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 8 [0x8]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 8 [0x8]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 24 [0x18]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 24 [0x18]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 32 [0x20]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 32 [0x20]))
ret_val false 

menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_can_eliminate
menmic_can_eliminate
menmic_frame_pointer_required_p
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 4 [0x4]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 20 [0x14]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 20 [0x14]))
ret_val false 

mov SI:
(reg:SI 8 r8)
(const_int 28 [0x1c])

mov SI:
(reg:SI 8 r8)
(const_int 4 [0x4])

mov SI:
(reg:SI 8 r8)
(const_int 20 [0x14])

mov SI:
(reg:SI 9 r9)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 4 [0x4])) [0 %sfp+4 S4 A32])
after:
(reg:SI 9 r9)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

mov SI:
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 28 [0x1c])) [0 %sfp+28 S4 A32])
(reg:SI 9 r9)
after:
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])
(reg:SI 9 r9)

mov SI:
(reg:SI 8 r8)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 20 [0x14])) [0 %sfp+20 S4 A32])
after:
(reg:SI 8 r8)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 28 [0x1c]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 28 [0x1c]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 4 [0x4]))
ret_val false 

mov SI:
(reg:SI 9 r9)
(const_int 28 [0x1c])

mov SI:
(reg:SI 9 r9)
(const_int 4 [0x4])

mov SI:
(reg:SI 10 r10)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 28 [0x1c])) [0 %sfp+28 S4 A32])
after:
(reg:SI 10 r10)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

mov SI:
(reg:SI 9 r9)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 4 [0x4])) [0 %sfp+4 S4 A32])
after:
(reg:SI 9 r9)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 32 [0x20]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 32 [0x20]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 8 [0x8]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 8 [0x8]))
ret_val false 

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 24 [0x18]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 24 [0x18]))
ret_val false 

mov SI:
(reg:SI 10 r10)
(const_int 32 [0x20])

mov SI:
(reg:SI 10 r10)
(const_int 8 [0x8])

mov SI:
(reg:SI 10 r10)
(const_int 24 [0x18])

mov SI:
(reg:SI 9 r9)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 8 [0x8])) [0 %sfp+8 S4 A32])
after:
(reg:SI 9 r9)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

mov SI:
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 32 [0x20])) [0 %sfp+32 S4 A32])
(reg:SI 9 r9)
after:
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])
(reg:SI 9 r9)

mov SI:
(reg:SI 10 r10)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 24 [0x18])) [0 %sfp+24 S4 A32])
after:
(reg:SI 10 r10)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

menmic_legitimate_address_p
mode: (SI) (strict)  (reload_in_progress) (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 32 [0x20]))
ret_val false 

menmic_regno_ok_for_base_p: return: 18
menmic_legitimate_address_p
mode: (SI)   (reload_in_progress) (reg_renumber): (r49 ---> r0)
address: 
(plus:SI (reg:SI 49)
    (const_int 32 [0x20]))
ret_val false 

mov SI:
(reg:SI 9 r9)
(const_int 32 [0x20])

mov SI:
(reg:SI 9 r9)
(mem/c:SI (plus:SI (reg/f:SI 18 r18)
        (const_int 32 [0x20])) [0 %sfp+32 S4 A32])
after:
(reg:SI 9 r9)
(mem:SI (reg/f:SI 18 r18) [0 S4 A32])

menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_regs_to_save
offset = 60 
menmic_initial_elimination_offset
menmic_legitimate_address_p
mode: (SI)  (reload_completed)  (reg_renumber): (r18 ---> r18)
address: 
(plus:SI (reg/f:SI 18 r18)
    (const_int 4 [0x4]))
ret_val false 


fail.c: In function 'fail':
fail.c:4:1: internal compiler error: in change_address_1, at emit-rtl.c:1933
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://gcc.gnu.org/bugs.html> for instructions.

next             reply	other threads:[~2012-06-04  7:37 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-04  7:37 Setjem Setjem [this message]
  -- strict thread matches above, loose matches on Subject: below --
2012-06-01 14:16 Setjem Setjem
2012-06-01 14:56 ` Ian Lance Taylor
2012-06-01 12:00 Setjem Setjem
2012-06-01 12:38 ` Georg-Johann Lay

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