* Machine description for volatile memory access
@ 2019-09-09 14:49 William Tambe
2019-09-09 15:21 ` Segher Boessenkool
0 siblings, 1 reply; 4+ messages in thread
From: William Tambe @ 2019-09-09 14:49 UTC (permalink / raw)
To: gcc-help
Does GCC support machine description for volatile memory accesses that
must not be cached ?
In other words, when using expressions such as theses, volatile memory
access instructions should be use:
volatile uint8_t *m;
uint8_t n;
*m = 5; // Should use a volatile memory store instruction.
n = *m; // Should use a volatile memory load instruction.
If GCC has support for the above, are there any examples I could be
pointed to in the sources ?
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Machine description for volatile memory access
2019-09-09 14:49 Machine description for volatile memory access William Tambe
@ 2019-09-09 15:21 ` Segher Boessenkool
2019-09-09 16:29 ` William Tambe
0 siblings, 1 reply; 4+ messages in thread
From: Segher Boessenkool @ 2019-09-09 15:21 UTC (permalink / raw)
To: William Tambe; +Cc: gcc-help
On Mon, Sep 09, 2019 at 09:48:46AM -0500, William Tambe wrote:
> Does GCC support machine description for volatile memory accesses that
> must not be cached ?
> In other words, when using expressions such as theses, volatile memory
> access instructions should be use:
>
> volatile uint8_t *m;
> uint8_t n;
>
> *m = 5; // Should use a volatile memory store instruction.
> n = *m; // Should use a volatile memory load instruction.
>
> If GCC has support for the above, are there any examples I could be
> pointed to in the sources ?
There is no such thing as a "volatile memory load" (or store). What is
it you really want to do?
"volatile" is a concept in the C language. It doesn't translate to machine
instructions very well. You might want to use support for atomic (via
builtins for example), or write assembler (or inline asm).
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Machine description for volatile memory access
2019-09-09 15:21 ` Segher Boessenkool
@ 2019-09-09 16:29 ` William Tambe
2019-09-09 16:37 ` Jeff Law
0 siblings, 1 reply; 4+ messages in thread
From: William Tambe @ 2019-09-09 16:29 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-help
On Mon, Sep 9, 2019 at 10:21 AM Segher Boessenkool
<segher@kernel.crashing.org> wrote:
>
> On Mon, Sep 09, 2019 at 09:48:46AM -0500, William Tambe wrote:
> > Does GCC support machine description for volatile memory accesses that
> > must not be cached ?
> > In other words, when using expressions such as theses, volatile memory
> > access instructions should be use:
> >
> > volatile uint8_t *m;
> > uint8_t n;
> >
> > *m = 5; // Should use a volatile memory store instruction.
> > n = *m; // Should use a volatile memory load instruction.
> >
> > If GCC has support for the above, are there any examples I could be
> > pointed to in the sources ?
>
> There is no such thing as a "volatile memory load" (or store). What is
> it you really want to do?
I would like to be able to detect in the machine description that a
memory load or store is being done for a volatile memory location.
>
> "volatile" is a concept in the C language. It doesn't translate to machine
> instructions very well. You might want to use support for atomic (via
> builtins for example), or write assembler (or inline asm).
All I am looking for, is whether the "volatile" attribute can be
detected from the machine description.
>
>
> Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Machine description for volatile memory access
2019-09-09 16:29 ` William Tambe
@ 2019-09-09 16:37 ` Jeff Law
0 siblings, 0 replies; 4+ messages in thread
From: Jeff Law @ 2019-09-09 16:37 UTC (permalink / raw)
To: William Tambe, Segher Boessenkool; +Cc: gcc-help
On 9/9/19 10:28 AM, William Tambe wrote:
> On Mon, Sep 9, 2019 at 10:21 AM Segher Boessenkool
> <segher@kernel.crashing.org> wrote:
>>
>> On Mon, Sep 09, 2019 at 09:48:46AM -0500, William Tambe wrote:
>>> Does GCC support machine description for volatile memory accesses that
>>> must not be cached ?
>>> In other words, when using expressions such as theses, volatile memory
>>> access instructions should be use:
>>>
>>> volatile uint8_t *m;
>>> uint8_t n;
>>>
>>> *m = 5; // Should use a volatile memory store instruction.
>>> n = *m; // Should use a volatile memory load instruction.
>>>
>>> If GCC has support for the above, are there any examples I could be
>>> pointed to in the sources ?
>>
>> There is no such thing as a "volatile memory load" (or store). What is
>> it you really want to do?
>
> I would like to be able to detect in the machine description that a
> memory load or store is being done for a volatile memory location.
>
>>
>> "volatile" is a concept in the C language. It doesn't translate to machine
>> instructions very well. You might want to use support for atomic (via
>> builtins for example), or write assembler (or inline asm).
>
> All I am looking for, is whether the "volatile" attribute can be
> detected from the machine description.
You can detect volatile on a MEM expression via
MEM_VOLATILE_P (mem). It's documented in the developer manual.
But odds are if you're using it in a target description, then you're
tackling the wrong problem in the wrong place.
jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-09-09 14:49 Machine description for volatile memory access William Tambe
2019-09-09 15:21 ` Segher Boessenkool
2019-09-09 16:29 ` William Tambe
2019-09-09 16:37 ` Jeff Law
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