prevent zero-extension when using a memory load instruction

prevent zero-extension when using a memory load instruction

[William Tambe]

In the machine description file, is there a way to tell GCC that a
memory load instruction already zero-extend such that it does not try
to apply zero-extension ?

Re: prevent zero-extension when using a memory load instruction

[Marc Glisse]

On Sat, 18 Apr 2020, William Tambe via Gcc-help wrote:

> In the machine description file, is there a way to tell GCC that a
> memory load instruction already zero-extend such that it does not try
> to apply zero-extension ?

I would look at it the other way around: you can tell GCC what asm to 
generate for a zero_extend with a memory operand. Or did you have a 
specific example in mind?

-- 
Marc Glisse

Re: prevent zero-extension when using a memory load instruction

[William Tambe]

On Sat, Apr 18, 2020 at 11:32 AM Marc Glisse <marc.glisse@inria.fr> wrote:
>
> On Sat, 18 Apr 2020, William Tambe via Gcc-help wrote:
>
> > In the machine description file, is there a way to tell GCC that a
> > memory load instruction already zero-extend such that it does not try
> > to apply zero-extension ?
>
> I would look at it the other way around: you can tell GCC what asm to
> generate for a zero_extend with a memory operand. Or did you have a

Thanks; tried above, but GCC still prefer a memory load followed by
zero-extension.

The example code used is as follow:

    unsigned char var;
    int main() {
        return var;
    }

Also tried x86 and ARM GCC port to see what they produce, and find
that only x86 will not generate a zero-extension when -Os is used.

The version of GCC used is 9.2.0.

Any other suggestions on how to tell GCC not to zero-extend the result
of a memory load ?

> specific example in mind?
>
> --
> Marc Glisse

Re: prevent zero-extension when using a memory load instruction

[Jeff Law]

On Sat, 2020-04-18 at 14:36 -0400, William Tambe via Gcc-help wrote:
> On Sat, Apr 18, 2020 at 11:32 AM Marc Glisse <marc.glisse@inria.fr> wrote:
> > On Sat, 18 Apr 2020, William Tambe via Gcc-help wrote:
> > 
> > > In the machine description file, is there a way to tell GCC that a
> > > memory load instruction already zero-extend such that it does not try
> > > to apply zero-extension ?
> > 
> > I would look at it the other way around: you can tell GCC what asm to
> > generate for a zero_extend with a memory operand. Or did you have a
> 
> Thanks; tried above, but GCC still prefer a memory load followed by
> zero-extension.
> 
> The example code used is as follow:
> 
>     unsigned char var;
>     int main() {
>         return var;
>     }
> 
> Also tried x86 and ARM GCC port to see what they produce, and find
> that only x86 will not generate a zero-extension when -Os is used.
> 
> The version of GCC used is 9.2.0.
> 
> Any other suggestions on how to tell GCC not to zero-extend the result
> of a memory load ?
Many ports have this feature and it's discussed in the developer documentation. 
Please read it.

jeff

Re: prevent zero-extension when using a memory load instruction

[Segher Boessenkool]

Hi!

On Sat, Apr 18, 2020 at 11:12:15AM -0400, William Tambe via Gcc-help wrote:
> In the machine description file, is there a way to tell GCC that a
> memory load instruction already zero-extend such that it does not try
> to apply zero-extension ?

At least on a load-store architecture (like a usual RISC), you get best
results if you make a separate pattern for that, and then let combine
combine the zero_extend with the load.


Segher

Re: prevent zero-extension when using a memory load instruction

[William Tambe]

On Mon, Apr 20, 2020 at 5:50 AM Segher Boessenkool
<segher@kernel.crashing.org> wrote:
>
> Hi!
>
> On Sat, Apr 18, 2020 at 11:12:15AM -0400, William Tambe via Gcc-help wrote:
> > In the machine description file, is there a way to tell GCC that a
> > memory load instruction already zero-extend such that it does not try
> > to apply zero-extension ?
>
> At least on a load-store architecture (like a usual RISC), you get best
> results if you make a separate pattern for that, and then let combine
> combine the zero_extend with the load.

I tried creating zero_extend pattern that could move data from memory
to a register (aka memory load), however GCC never used it and
preferred using memory load followed by a zero-extend.

Any other suggestions ? I have been googling around with no solution in sight.

>
>
> Segher

Re: prevent zero-extension when using a memory load instruction

[Segher Boessenkool]

Hi!

On Mon, Apr 20, 2020 at 10:36:35AM -0400, William Tambe via Gcc-help wrote:
> > > In the machine description file, is there a way to tell GCC that a
> > > memory load instruction already zero-extend such that it does not try
> > > to apply zero-extension ?
> >
> > At least on a load-store architecture (like a usual RISC), you get best
> > results if you make a separate pattern for that, and then let combine
> > combine the zero_extend with the load.
> 
> I tried creating zero_extend pattern that could move data from memory
> to a register (aka memory load), however GCC never used it and
> preferred using memory load followed by a zero-extend.

Use -dap and look at the dump files; see what happened?  You often get
it done by expand already (which isn't such a great idea, but hey), but
some cases are done by combine as well.  If you get separate load and
extend insns generated, you can look at the combine dump to see why
those insns didn't combine there.


Segher