From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id 8E209385840C for ; Fri, 28 Jan 2022 18:24:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8E209385840C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 20SIL6qq027563; Fri, 28 Jan 2022 12:21:06 -0600 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 20SIL5Pv027562; Fri, 28 Jan 2022 12:21:05 -0600 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Fri, 28 Jan 2022 12:21:05 -0600 From: Segher Boessenkool To: Jeff Law Cc: Reshabh K Sharma , gcc-help@gcc.gnu.org Subject: Re: Describe instructions with same reg in def and use or mutiple defs and attach write latency Message-ID: <20220128182105.GF614@gate.crashing.org> References: <3b7e6310-1376-91a0-fe50-a6b7e5dd125b@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3b7e6310-1376-91a0-fe50-a6b7e5dd125b@gmail.com> User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Jan 2022 18:24:13 -0000 On Fri, Jan 28, 2022 at 10:39:54AM -0700, Jeff Law via Gcc-help wrote: > On 1/26/2022 6:20 PM, Reshabh K Sharma via Gcc-help wrote: > >I am trying to implement a post address update load instruction in our > >downstream riscv backend. I want to attach write latency information to a > >use register. For example, rd = new_load rs1 rs2, I want to attach separate > >write latency information to both rd and rs1. > > > >I am unable to find how to describe instructions that have an operand as > >both def and use, and later attach write latency information for the > >instruction scheduler to work properly. > > > >It will also be very helpful if you can point me to the implementation of > >similar instructions in other backends, for example, LBZU in PowerPC, ARM's > >LWD post/pre address update versions and ARM's neon simd load with update. > I'm not sure the scheduler can model different latencies for the > multiple outputs.  If anyone knows for sure, it would be Vlad. You can use TARGET_SCHED_ADJUST_COST? > It may not matter in practice though.  I'd hazard a guess these things > hang out in the reorder buffer until both outputs are ready and only > then will it move into the retirement queue. The GCC scheduling description says when results are ready, not when the instructions (can) finish or complete (aka retire). I do agree this case doesn't matter so much, cases where it does matter will have their dependency chains broken much earlier :-) Segher