From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 67F053858C56 for ; Thu, 16 Jun 2022 09:06:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 67F053858C56 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 27C4512FC; Thu, 16 Jun 2022 02:06:52 -0700 (PDT) Received: from [10.57.41.51] (unknown [10.57.41.51]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 72ED33F7F5; Thu, 16 Jun 2022 02:06:51 -0700 (PDT) Message-ID: <22364bdc-6cb5-b612-b3fa-bbb7476bcc7c@foss.arm.com> Date: Thu, 16 Jun 2022 10:06:49 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: A ARM target question Content-Language: en-GB To: Stefan Ring , "gcc-help@gcc.gnu.org" References: From: Richard Earnshaw In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3492.1 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, NICE_REPLY_A, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Jun 2022 09:06:53 -0000 On 15/06/2022 18:31, Stefan Ring via Gcc-help wrote: > On Tue, Jun 14, 2022 at 6:58 AM Gary Oblock via Gcc-help > wrote: >> >> What is the target specification for a ARMv8.2A? I'm trying to build a cross compiler >> that can emit Thumb2 instructions for this architectue. > > Are you talking about 32bit arm or aarch64? ARMv8.2A sounds like 64 > bits, but Thumb2 sounds like 32 bits. Armv8 supports both AArch32 (32-bit) and AArch64 (64-bit) execution states. To generate code for AArch32 you'll need the 'arm' configurations of GCC. The 'aarch64' configuration can only generate code for 64-bit state. R.