Register Usage

Register Usage

[John Farmer]

Hi,

I am trying to understand how the general purpose registers are used by the
GCC compiler. Most I have been able to work out but have these questions.

Register R12 is initialised in my startup code to the same value as the SP
(R13) but it never appears to be used for anything. Whats the purpose of
this register?

I have looked at the ARM and THUMB procedure call standard (briefly) and it
looks as though R7 is the Thumb-state Work register or variable register.
However, looking at the assembly code produced for functions it is clearly
being used as the frame pointer. Why is there a difference?

Is there a defining text somewhere that details GCC register usage when
compiling for a Cortex-M3 chip?

I am using GCC V4.1.1 and a STM32F103RB (Cortex-M3) microcontroller.

Regards


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Re: Register Usage

[Ian Lance Taylor]

John Farmer <news02@lavabit.com> writes:

> Register R12 is initialised in my startup code to the same value as the SP
> (R13) but it never appears to be used for anything. Whats the purpose of
> this register?
>
> I have looked at the ARM and THUMB procedure call standard (briefly) and it
> looks as though R7 is the Thumb-state Work register or variable register.
> However, looking at the assembly code produced for functions it is clearly
> being used as the frame pointer. Why is there a difference?
>
> Is there a defining text somewhere that details GCC register usage when
> compiling for a Cortex-M3 chip?

gcc follows the various ARM ABIs, which are documented on arm.com.  I
don't know which particular ABI you are using--it depends upon how gcc
was configured.

r12 is known as ip.  gcc will use it as a temporary general purpose
register.  It is also used in the prologue to set up the stack frame; I
think this use may be mandated by the ABI, but I'm not sure.

r7 is used as the frame pointer in Thumb code because r12 is not
accessible for general use.

By the way, make sure you are looking at optimized code.

Ian

Re: Register Usage

[John Farmer]

Hi Ian thanks for the reply,

I had a good look through the ARM-THUMB Procedure Call Standard and it sort
of suggests that R7 could be used as a frame pointer. Looked through the GCC
docs and found the -fabi option but it appears to apply to C++ code.

I am still wondering what makes the decision to use R7 as the frame pointer.
If its used because of an ABI standard for the ARM Cortex-M3 CPU how is it
specified to GCC? Also if this is the case is there a standard that I could
look through? I have looked on the ARM web site but not found it yet.

Regards John

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Re: Register Usage

[Ian Lance Taylor]

John Farmer <news02@lavabit.com> writes:

> I had a good look through the ARM-THUMB Procedure Call Standard and it sort
> of suggests that R7 could be used as a frame pointer. Looked through the GCC
> docs and found the -fabi option but it appears to apply to C++ code.
>
> I am still wondering what makes the decision to use R7 as the frame pointer.
> If its used because of an ABI standard for the ARM Cortex-M3 CPU how is it
> specified to GCC? Also if this is the case is there a standard that I could
> look through? I have looked on the ARM web site but not found it yet.

When gcc needs a frame pointer in Thumb code, it will always use r7.
There is no way to change this.  I'm not sure why you would want to
change it.

Ian

Re: Register Usage

[John Farmer]

Hi Ian,

I do not want to change to another register for R7 just wondered how the
decission was made to use it in the first place. Was it because Thumb = R7
or because the GCC adheres to some specification that states it must use R7.
If there is such a specification where abouts could I find it?

Regards John
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Re: Register Usage

[Richard Earnshaw]

On Tue, 2009-04-28 at 15:06 -0700, John Farmer wrote:
> Hi Ian thanks for the reply,
> 
> I had a good look through the ARM-THUMB Procedure Call Standard and it sort
> of suggests that R7 could be used as a frame pointer. Looked through the GCC
> docs and found the -fabi option but it appears to apply to C++ code.
> 

The ARM-THUMB Procedure Call standard was superseded by "The ABI for the
ARM Architecture" nearly 5 years ago now, you can obtain the most recent
documents from the ARM documentation website:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.swdev/index.html

The current PCS is supported in gcc by several configurations (most of
which have 'eabi' somewhere in the configuration name; for Cortex-m3 I
strongly recommend you use one of those configurations.  You might also
want to configure the compiler with "--with-isa=thumb" and
"--with-cpu=cortex-m3"; this will save you from having to modify your
configure scripts or compiler command lines every time you build some
code.

> I am still wondering what makes the decision to use R7 as the frame pointer.
> If its used because of an ABI standard for the ARM Cortex-M3 CPU how is it
> specified to GCC? Also if this is the case is there a standard that I could
> look through? I have looked on the ARM web site but not found it yet.

The procedure call standards do not specify a frame pointer any more
(and haven't for nearly 15 years -- ie since Thumb was added to the
architecture).  So any compiler using a frame pointer is free to use
whatever register is wishes to.  In thumb you want to avoid using a
frame pointer whenever possible since non-stack based addressing is
severely limited in the offsets that are permitted.

R.

Re: Register Usage

[John Farmer]

Hi Richard,

I have downloaded the docs and am having a browse now, thanks.

I did export the projects build file and searched it for "abi" but only
found "-mfloat-abi=soft" which specifies an ABI for floating point values.
There is a GCC option "-mabi=name" but that does not appear anywhere in my
command lines. Given that the -mabi option is not present presumably I am
using a default ABI, but what is it?

Is there a way to get GCC to display all of its default options that it uses
when for example certain comman line options are not specified?

Regards John
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Re: Register Usage

[Richard Earnshaw]

On Wed, 2009-04-29 at 03:18 -0700, John Farmer wrote:
> Hi Richard,
> 
> I have downloaded the docs and am having a browse now, thanks.
> 
> I did export the projects build file and searched it for "abi" but only
> found "-mfloat-abi=soft" which specifies an ABI for floating point values.
> There is a GCC option "-mabi=name" but that does not appear anywhere in my
> command lines. Given that the -mabi option is not present presumably I am
> using a default ABI, but what is it?
> 

The short answer is that it depends on your compiler's configuration; if
you used arm-none-eabi (which is what I would recommend for bare-metal
use on a CPU like Cortex-m3), then it will be based on the new ABI.

> Is there a way to get GCC to display all of its default options that it uses
> when for example certain comman line options are not specified?

The only information that is printed comes out with --help (you'll get
more detailed help if you also specify a source file of the language you
want help for), or what you can find in the manual.

R.

Re: Register Usage

[John Farmer]

Hi Richard,

Applogies if this sounds silly but I am new to the GCC toolchain.

Are you saying that arm-none-eab is a type of compiler and not a command
line option? 

The GCC tools "as" and "cc1" that I have are part of the development IDE
(CrossWorks for ARM) that I am using and are based on GCC V4.1.1. 

Would I be correct in thinking that "as" and "cc1" would have been built
specifically for the ARM CPU? Looking at the --help for these the only CPU
options shown are for the ARM which presumably suggests that many (non-ARM)
options have been removed.

Regards John
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Re: Register Usage

[Richard Earnshaw]

On Wed, 2009-04-29 at 05:14 -0700, John Farmer wrote:
> Hi Richard,
> 
> Applogies if this sounds silly but I am new to the GCC toolchain.
> 
> Are you saying that arm-none-eab is a type of compiler and not a command
> line option? 

Yes, when you build GCC from the sources you get to determine both what
machine you want to target (ARM, MIPS, Sparc, etc) and what sort of
platform will be running on your machine (Linux, Solaris, bare-metal (ie
no OS).  You can find out what configuration was used for your
particular compiler if you invoke GCC with just the -v option.  For
example, a compiler I have here says:

[RWE]$ arm-eabi-gcc -v
Target: arm-eabi
Configured with: /home/rearnsha/gnusrc/gcc-cross/trunk/configure
--prefix=/work/rearnsha/gnu/trunk/testinstall --enable-checking=release
--disable-werror --enable-languages=c,c++ --target=arm-eabi
--with-headers=/home/rearnsha/gnusrc/gcc-cross/trunk/newlib/libc/include
--with-newlib --disable-libmudflap
--with-gmp=/home/rearnsha/gnu/install/x86
Thread model: single
gcc version 4.4.0 20081112 (experimental) (GCC) 

> 
> The GCC tools "as" and "cc1" that I have are part of the development IDE
> (CrossWorks for ARM) that I am using and are based on GCC V4.1.1. 
> 

If your target isn't for the EABI (see above), then I think you'll need
to talk to the CrossWorks people to find out how to get one.

> Would I be correct in thinking that "as" and "cc1" would have been built
> specifically for the ARM CPU? Looking at the --help for these the only CPU
> options shown are for the ARM which presumably suggests that many (non-ARM)
> options have been removed.

Indeed (see above).

R.

Re: register usage

[Andrew Haley]

Petar Bajic writes:
 > 
 > 
 > For this, I had to make two new register classes (machine has 32 regs and 
 > basicly just one reg class GENERAL_REGS)
 > I added two new classes: HI_REGS, and LO_REGS to "enum reg_classes" wich are 
 > lower and higher 16 regs of GENERAL_REGS.
 > REG_CLASS_CONTENTS is expanded with { 0xffff0000 } and { 0x0000ffff }
 > REG_CLASS_NAMES has two more names "HI_REGS" and "LO_REGS"
 > 
 > in machine.c file I modified  "reg_class_from_letter"  making letter 'j' and 
 > 'k' return HI_REGS and LO_REGS
 > 
 > in machine.md I finally wrote a rule that uses j and k regs to distinct 
 > input and output....
 > (define_insn "*movsicc_insn"
 >   [(set (match_operand:SI 0 "register_operand" "=j,j")
 >  (if_then_else:SI (match_operator 1 "comparison_operator" [(match_operand:SI 
 > 4 "register_operand" "=k,k") (const_int 0)])
 >     (match_operand:SI 2 "register_operand" "=d,d")
 >     (match_operand:SI 3 "register_operand" "=d,d")))]
 >   ""
 > "..."
 > 
 > and the error is:
 > ../../gcc/libgcc2.c:785: internal compiler error: in copy_to_mode_reg, at 
 > explow.c:581
 > 
 > what else do I have to do for this to work?

I would look in the debugger to see what copy_to_mode_reg was trying
to do.  

I suspect you haven't defined a pattern to move into one of the
register classes.

Andrew.

Re: register usage

[Petar Bajic]

----- Original Message ----- 
From: "Andrew Haley" <aph@redhat.com>
To: "Petar Bajic" <petar.bajic@micronasnit.com>
Cc: <gcc-help@gcc.gnu.org>
Sent: Wednesday, July 12, 2006 2:48 PM
Subject: Re: register usage


> Petar Bajic writes:
> > I want to forbid compiler to use condition register for destination in 
> > movz
> > instruction
> > instruction (if r3 == 0, move r2 to r1) should look like this:
> > movz r1, r2, r3  (r3 condition, r2 source, r1 destination register)
> > but compiler generates this
> > movz r3, r2, r3
> > and uses r3 further on. Wich is techincally ok, but I have this problem 
> > with
> > overwritting condition and would like to save it.
> > How do I tell compiler to generate different register for destination?
>
> Put the condition code register in a different class from the other
> registers.
>
> Andrew.
>

For this, I had to make two new register classes (machine has 32 regs and 
basicly just one reg class GENERAL_REGS)
I added two new classes: HI_REGS, and LO_REGS to "enum reg_classes" wich are 
lower and higher 16 regs of GENERAL_REGS.
REG_CLASS_CONTENTS is expanded with { 0xffff0000 } and { 0x0000ffff }
REG_CLASS_NAMES has two more names "HI_REGS" and "LO_REGS"

in machine.c file I modified  "reg_class_from_letter"  making letter 'j' and 
'k' return HI_REGS and LO_REGS

in machine.md I finally wrote a rule that uses j and k regs to distinct 
input and output....
(define_insn "*movsicc_insn"
  [(set (match_operand:SI 0 "register_operand" "=j,j")
 (if_then_else:SI (match_operator 1 "comparison_operator" [(match_operand:SI 
4 "register_operand" "=k,k") (const_int 0)])
    (match_operand:SI 2 "register_operand" "=d,d")
    (match_operand:SI 3 "register_operand" "=d,d")))]
  ""
"..."

and the error is:
../../gcc/libgcc2.c:785: internal compiler error: in copy_to_mode_reg, at 
explow.c:581

what else do I have to do for this to work?

Re: register usage

[Andrew Haley]

Petar Bajic writes:
 > I want to forbid compiler to use condition register for destination in movz 
 > instruction
 > instruction (if r3 == 0, move r2 to r1) should look like this:
 > movz r1, r2, r3  (r3 condition, r2 source, r1 destination register)
 > but compiler generates this
 > movz r3, r2, r3
 > and uses r3 further on. Wich is techincally ok, but I have this problem with 
 > overwritting condition and would like to save it.
 > How do I tell compiler to generate different register for destination?

Put the condition code register in a different class from the other
registers.  

Andrew.

register usage

[Petar Bajic]

I want to forbid compiler to use condition register for destination in movz 
instruction
instruction (if r3 == 0, move r2 to r1) should look like this:
movz r1, r2, r3  (r3 condition, r2 source, r1 destination register)
but compiler generates this
movz r3, r2, r3
and uses r3 further on. Wich is techincally ok, but I have this problem with 
overwritting condition and would like to save it.
How do I tell compiler to generate different register for destination?

Petar