Re: Emission of store_multiple and load_multiple patterns

[noeljohn <noel.daniel@gmx.com>]

Ian Lance Taylor-3 wrote:
> 
> noeljohn <noel.daniel@gmx.com> writes:
> 
>> Ian Lance Taylor-3 wrote:
>>> 
>>> noeljohn <noel.daniel@gmx.com> writes:
>>> 
>>>>   The array as I have seen is not being treated as a vector. What it
>>>> does
>>>> is
>>>> it directly loads the integer array data into the stack. This is
>>>> normally
>>>> done for processors which does not have a support for multiple loading
>>>> and
>>>> storing of words. Is there any way by which we can convey gcc through
>>>> macros
>>>> that our architecture supports this multiple loading and storing
>>>> facility?
>>> 
>>> I'm sorry, I don't understand what you mean.  What specific
>>> instruction are you trying to generate, and what precisely does it do?
>>> When exact C code would you write that you would expect to generate
>>> this instruction?
>>> 
>>> Ian
>>> 
>>> 
>>
>> Hello Sir,
>>     The actual problem is that the array contents are not put in a
>> separate
>> data section we would see in .s file. Suppose we take a arm processor or
>> rs6000 processor, a separate section will be created in which the array
>> contents will be stored and then these array contents are loaded into the
>> stack. I want this data section to be created. How should I go forward ?
> 
> 
> Give us an example.  Show us some source code.
> 
> Ian
> 
> 


	.file	"1234.c"

	.section	.rodata

	.align	2

	.type	C.0.1175, %object

	.size	C.0.1175, 20

C.0.1175:

	.word	6

	.word	9

	.word	5

	.word	6

	.word	8

	.text

	.align	2

	.global	main

	.type	main, %function

main:

	@ args = 0, pretend = 0, frame = 20

	@ frame_needed = 1, uses_anonymous_args = 0

	mov	ip, sp

	stmfd	sp!, {r4, fp, ip, lr, pc}

	sub	fp, ip, #4

	sub	sp, sp, #20

	ldr	r3, .L3

	sub	r4, fp, #36

	mov	ip, r3

	ldmia	ip!, {r0, r1, r2, r3}

	stmia	r4!, {r0, r1, r2, r3}

	ldr	r3, [ip, #0]

	str	r3, [r4, #0]

	ldr	r2, [fp, #-28]

	ldr	r3, [fp, #-20]

	and	r3, r2, r3

	str	r3, [fp, #-24]

	sub	sp, fp, #16

	ldmfd	sp, {r4, fp, sp, pc}

.L4:

	.align	2

.L3:

	.word	C.0.1175

	.size	main, .-main

	.ident	"GCC: (GNU) 4.3.0"


This is the arm assembly for the c program:
void main()

{

int a[5]={6,9,5,6,8};

a[3]=a[2] & a[4];

}

The section below is the one which needs to be generated for the machine
which I am working for.

	.section	.rodata
	.align	2
	.type	C.0.1175, %object
	.size	C.0.1175, 20
C.0.1175:
	.word	6
	.word	9
	.word	5
	.word	6
	.word	8
 
Similar section is seen for the assembly generated by the machine powerpc.
How can it be generated?

noeljohn
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