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* using variables in makefile
@ 2010-03-04 14:58 mahmoodn
  2010-03-04 15:28 ` John (Eljay) Love-Jensen
  0 siblings, 1 reply; 3+ messages in thread
From: mahmoodn @ 2010-03-04 14:58 UTC (permalink / raw)
  To: gcc-help


In my makefile I have these lines:
GPGPUSIM_ROOT := $(GPGPUSIM_ROOT)
include $(NVIDIA_CUDA_SDK_LOCATION)/C/common/common.mk

I have set two variables in bash.rc file. The results for echo are:
mahmood@magma:~$ echo $GPGPUSIM_ROOT
/home/mahmood/gpgpusim/gpgpu-sim_v2.1.1b

mahmood@magma:~$ echo $NVIDIA_CUDA_SDK_LOCATION
/home/mahmood/NVIDIA_GPU_Computing_SDK

Now when I run the makefile I get this error:
Makefile:<line number>: /C/common/common.mk: No such file or directory
make: *** No rule to make target `/C/common/common.mk'.  Stop.

I have searched to find why environment variables don't work in makefile,
but didn't find anything useful. I am not expert in makefile structures but
I have compiled makefiles that contain 
-I$(VARIABLE)/include and they are successfull. So what is the difference
here?

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2010-03-04 14:58 using variables in makefile mahmoodn
2010-03-04 15:28 ` John (Eljay) Love-Jensen
2010-03-05  7:07   ` mahmoodn

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