From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id EC6C4385BF9C for ; Fri, 28 Jan 2022 17:39:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EC6C4385BF9C Received: by mail-pl1-x634.google.com with SMTP id j16so6712173plx.4 for ; Fri, 28 Jan 2022 09:39:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:references:from:in-reply-to :content-transfer-encoding; bh=OjytpCfwgqTW0scppw5vb5KVwM6S3Bq826zONYZewiw=; b=L0cGzqBZT+iBiKKtnRYtOcACM4XjITFIZFcRoP5QqqPNMbPazrtBHLqAbJiLmIDMwT y5tsBx29U/evFUTm/Rnz/8c9pdwnP/zQmRJR+//U7fDwxT3QuZPgH4TpVqj5syc1DPJ0 gZl24YyMEgKd38n4n4d1gu6ox6otaut1Rfh1LgX8gbgccXzTuNvKVW/hvedg8xWgZjzi GxISfGKudoB+hs6YrIXaHJYM7LcZuet5M8aufxnv0+6F+AANpcGr1W59s0GDw2I8LrmI BFLsIc18yioC3lSf9V00D4f0xwDQHP26l/3tk2Pdggi6bZDdyYYmiqM19OfaukE1TD/7 2T3A== X-Gm-Message-State: AOAM532ZvLLN6NIDCCYuAF9ft0SR5jU93Yov/glbCcO34ARYHfIALtFP cTUd+hBPWmbVeOIWShHWdj1zNgWi0RPCYg== X-Google-Smtp-Source: ABdhPJyr2w7+ZSsSaFi09PD1QifQPmNsmDwYXdKOI226PVu4bHaVvYJqLrG0aPoX+lG6YFU0KuXKFA== X-Received: by 2002:a17:903:1109:: with SMTP id n9mr9343701plh.163.1643391597039; Fri, 28 Jan 2022 09:39:57 -0800 (PST) Received: from [192.168.1.15] (65-130-85-11.slkc.qwest.net. [65.130.85.11]) by smtp.gmail.com with ESMTPSA id m20sm7298683pfk.215.2022.01.28.09.39.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jan 2022 09:39:56 -0800 (PST) Message-ID: <3b7e6310-1376-91a0-fe50-a6b7e5dd125b@gmail.com> Date: Fri, 28 Jan 2022 10:39:54 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: Describe instructions with same reg in def and use or mutiple defs and attach write latency Content-Language: en-US To: Reshabh K Sharma , gcc-help@gcc.gnu.org References: From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Jan 2022 17:39:59 -0000 On 1/26/2022 6:20 PM, Reshabh K Sharma via Gcc-help wrote: > Hello everyone, > > I am trying to implement a post address update load instruction in our > downstream riscv backend. I want to attach write latency information to a > use register. For example, rd = new_load rs1 rs2, I want to attach separate > write latency information to both rd and rs1. > > I am unable to find how to describe instructions that have an operand as > both def and use, and later attach write latency information for the > instruction scheduler to work properly. > > It will also be very helpful if you can point me to the implementation of > similar instructions in other backends, for example, LBZU in PowerPC, ARM's > LWD post/pre address update versions and ARM's neon simd load with update. I'm not sure the scheduler can model different latencies for the multiple outputs.  If anyone knows for sure, it would be Vlad. It may not matter in practice though.  I'd hazard a guess these things hang out in the reorder buffer until both outputs are ready and only then will it move into the retirement queue. jeff