From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2C8873857838 for ; Tue, 13 Oct 2020 11:46:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 2C8873857838 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C38881FB; Tue, 13 Oct 2020 04:46:38 -0700 (PDT) Received: from [192.168.1.19] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2DCC23F719; Tue, 13 Oct 2020 04:46:38 -0700 (PDT) Subject: Re: Atomic accesses on ARM microcontrollers To: David Brown , Toby Douglass Cc: GCC help References: <945d5e74-b449-3746-6560-996d0437db76@hesbynett.no> <015e0ad8-8052-c63f-0eb1-4b9fa817cc10@hesbynett.no> <08ef1c04-8e03-5ae8-e070-0499984f21bd@hesbynett.no> <24c49c76-43c3-9a0d-6b02-a4340b1fccba@winterflaw.net> <10a7d64b-e7a4-60b3-0270-8469a8621333@hesbynett.no> From: Richard Earnshaw Message-ID: <3d5d0b46-b9dc-c6ed-7395-83fafbb8a838@foss.arm.com> Date: Tue, 13 Oct 2020 12:46:10 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <10a7d64b-e7a4-60b3-0270-8469a8621333@hesbynett.no> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3493.1 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, NICE_REPLY_A, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Oct 2020 11:46:40 -0000 On 11/10/2020 13:51, David Brown wrote: > > > On 11/10/2020 14:34, Toby Douglass wrote: >> On 11/10/2020 14:16, David Brown wrote: > >> >>>> I could be wrong, but I think the only way you can do this with atomics >>>> is copy-on-write.  Make a new copy of the data, and use an atomic to >>>> flip a pointer, so the readers move atomically from the old version to >>>> the new version. >>> >>> I've been thinking a bit more about this, inspired by your post here. >>> And I believe you are correct - neither ldrex/strex nor load/store >>> double register is sufficient for 64-bit atomic accesses on the 32-bit >>> ARM, even for plain reads and writes. >> >> No - I think you can have 64-bit atomic stores on a 32-bit CPU.  There >> *is* a double word atomic compare-and-swap. > > Certainly it is possible - if the cpu has such an instruction. The > Cortex-M cores do not. > >>   If you define a 64-bit >> integer type, and use it with __atomic_compare_exchange_n(), you should >> get a 64-bit atomic swap.  In older versions of the library, I actually >> had inline assembly for this, but I realised in the end I could in fact >> get GCC to emit the correct code. >> >> However, I don't understand how a double-word atomic store helps you.  >> If you have an arbitrarily-sized block of memory to update atomically, >> how can you use a 64-bit atomic store to do this? >> > > It would not help for arbitrary blocks of memory, but it /would/ help > for 64-bit blocks. And that would cover a sizeable majority of > use-cases for me. > >>> One thing we can all be sure about - this stuff is difficult, it needs a >>> /lot/ of thought, and the documentation is often poor on the critical >>> details. >> >> Amen. >> I think you've probably identified a real issue in the way we expand 64-bit volatile accesses on all AArch32 targets. If you have not already done so, please could you open a bugzilla ticket? R.