From: David Daney <ddaney@avtrex.com>
To: Pan ruochen <panruochen@gmail.com>
Cc: gcc-help@gcc.gnu.org
Subject: Re: Is it possible that gcc reorders a series of read/write operations?
Date: Mon, 08 Sep 2008 06:16:00 -0000 [thread overview]
Message-ID: <48C4C329.50704@avtrex.com> (raw)
In-Reply-To: <af0faace0809071901p4ba1b8f0r88acb8f992c15802@mail.gmail.com>
Pan ruochen wrote:
>> No.
>>
>> It is separate from the caches and was intended to coalesce adjacent writes
>> into a single wider write. It had the problem that it could end up
>> reordering the writes under some circumstances even through uncached
>> portions of the address space.
>>
>> David Daney
>>
>
> Is there any online document introducing hardware write reordering
> about MIPS? I want to have a read
> to get more details.
Each MIPS CPU is different. Read the hardware manual and errata for the
particular CPU you are interested in.
David Daney
prev parent reply other threads:[~2008-09-08 6:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-03 2:23 Pan ruochen
2008-09-03 2:46 ` me22
2008-09-03 4:15 ` Robert William Fuller
2008-09-03 12:28 ` Marco Manfredini
2008-09-03 16:20 ` David Daney
2008-09-04 1:12 ` Pan ruochen
2008-09-04 1:26 ` me22
2008-09-04 16:06 ` David Daney
2008-09-05 2:29 ` Pan ruochen
2008-09-05 4:01 ` David Daney
2008-09-08 2:01 ` Pan ruochen
2008-09-08 6:16 ` David Daney [this message]
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