From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 088D03971C38 for ; Thu, 10 Sep 2020 10:35:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 088D03971C38 Received: by mail-ej1-x632.google.com with SMTP id p9so7966311ejf.6 for ; Thu, 10 Sep 2020 03:35:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:content-transfer-encoding:from:mime-version :subject:date:message-id:references:cc:in-reply-to:to; bh=QGwaU4J+WWMRbtT8R2MpRkCS9BQmsRrTaos1EcuiaX4=; b=i8qWKvMAdM3ZLs7tiYCe4x4nXS8ww3ZzPdj0hNM7ucx6X41rerLXT0+jS1nQDEYwPI OJdRn7IKo4Hvl+iz5u37se/b/8TxoBgocxc1Bxwsug1IBcYEGEfKBo+Ya2LarTdMoyZY A71U/Y1iFwaXheIpSDsrM5COuzHRw7cIIe/muizMQrdbM6vIaLHVzarBUjnunCGG81h/ ZqwEEA96gK6zJ0wsKgau2lJTicozSxf+m7paqZQA72uGfarJgU1y0SkgS8zsg3B8kNZy pgUl8vUMNBrf/wfGLFSTuG0zlLzmFmZCUFRw0uO5blpxYA7heV5y6aU/lD99N9CSkNSi DEww== X-Gm-Message-State: AOAM531WJ5A5QWsySVEXeJhmwvw34hmBuiZeu66GvxqO/zil5VSCVXAo yCzKDczhZbxVxOinJeHIqhjTMGonbFs= X-Google-Smtp-Source: ABdhPJwr+ZxEKeVQ2jJZia4f/Vl5AVOCz33SxkB5AFE24D1XIQrfTNVByXanbubFpXY1p20B4wr7qA== X-Received: by 2002:a17:906:3785:: with SMTP id n5mr8586992ejc.218.1599734150892; Thu, 10 Sep 2020 03:35:50 -0700 (PDT) Received: from ?IPv6:2a00:20:9029:af15:5cd4:20dd:936c:36d1? ([2a00:20:9029:af15:5cd4:20dd:936c:36d1]) by smtp.gmail.com with ESMTPSA id l7sm6446179ejc.25.2020.09.10.03.35.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Sep 2020 03:35:50 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Jochen Barth Mime-Version: 1.0 (1.0) Subject: Re: arm_neon.h / vext_u64 (uint64x1_t __a, uint64x1_t __b, __const int __c) Date: Thu, 10 Sep 2020 12:35:48 +0200 Message-Id: <4AF21AB0-ACC1-474C-AF72-A78B6A02A1C4@gmail.com> References: Cc: gcc-help In-Reply-To: To: Tamar Christina X-Mailer: iPhone Mail (17G80) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Sep 2020 10:35:53 -0000 Thanks a lot! Regards, Jochen Von meinem iPhone gesendet > Am 10.09.2020 um 10:35 schrieb Tamar Christina : >=20 > =EF=BB=BFHi Jochen, >=20 >> -----Original Message----- >> From: Jochen Barth >> Sent: Thursday, September 10, 2020 9:14 AM >> To: Tamar Christina >> Cc: gcc-help >> Subject: Re: arm_neon.h / vext_u64 (uint64x1_t __a, uint64x1_t __b, >> __const int __c) >>=20 >> Dear Tamar, >>=20 >> Sorry, I do no get the point: >>=20 >>>>> EXT is a byte level extract, if you have a 64 bit vector and a >>>>> 64-bit type like uint64x1_t then the only possible index for n is 0. >>=20 >=20 > Because those intrinsics are not doing byte level extraction. They are con= venience functions that > do not allow partial extraction of a type. For instance vext_s16 which tak= es an int16x4_t as input > restricts the values of n to 0 to 3 because when used with the EXT instruc= tion it always > makes sure they're a multiple of 2 bytes since a int16 is two bytes. >=20 > A uint64x1_t is a vector of 8 bytes which the intrinsic does as a group of= 8 bytes since it > Always wants to extract whole numbers. As such the only possible index is 0= . >=20 > To get the behavior you have in your example you need to do the extraction= on bytes using > vext_u8 which will allow you to corrupt the number. i.e. >=20 > what you want is >=20 > vreinterpret_u64_u8 (vext_u8 (vreinterpret_u8_u64 (a), vreinterpret_u8_u64= (b), )) >=20 > where your extraction happens on bytes. In this case n has the range 0-7. >=20 > Instead of looking at the Arm ARM you should look at the definition of the= intrinsics > https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/in= trinsics >=20 > Regards, > Tamar >=20 >> But my previous examples with n=3Dc=3D1..7 showed that different (n=3Dc)'= s are >> possible, >>=20 >> why is "the only possible index for n=3D0" ? >>=20 >> Kind regards, Jochen