From: dw <limegreensocks@yahoo.com>
To: "gcc-help@gcc.gnu.org" <gcc-help@gcc.gnu.org>
Subject: Re: Question about __builtin_ia32_mfence and memory barriers
Date: Wed, 05 Jun 2013 02:45:00 -0000 [thread overview]
Message-ID: <51AEA657.9080607@yahoo.com> (raw)
In-Reply-To: <CAKOQZ8yxRncKoRjLcnR5rZnkybtOTAtCoLo9f-OJyCFe47JWEw@mail.gmail.com>
> A better choice these days is __atomic_thread_fence(__ATOMIC_SEQ_CST)
> (or __atomic_signal_fence).
This sounded so promising. Unfortunately, it's not producing the results
I need. I can put all these statements in the code, and none of them
generate -any- fence instruction:
__atomic_thread_fence(__ATOMIC_RELAXED);
__atomic_thread_fence(__ATOMIC_CONSUME);
__atomic_thread_fence(__ATOMIC_ACQUIRE);
__atomic_thread_fence(__ATOMIC_RELEASE);
__atomic_thread_fence(__ATOMIC_ACQ_REL);
__atomic_signal_fence(__ATOMIC_RELAXED);
__atomic_signal_fence(__ATOMIC_CONSUME);
__atomic_signal_fence(__ATOMIC_ACQUIRE);
__atomic_signal_fence(__ATOMIC_RELEASE);
__atomic_signal_fence(__ATOMIC_ACQ_REL);
__atomic_signal_fence(__ATOMIC_SEQ_CST);
And while I get an mfence instruction with this:
__atomic_thread_fence(__ATOMIC_SEQ_CST);
It doesn't produce quite the same instruction ordering as:
asm volatile ("mfence" ::: "memory");
Which makes me think that whatever __ATOMIC_SEQ_CST means, it's not the
same as the "memory" clobber. Also, I'm looking to support SFENCE and
LFENCE, which these don't appear to support at all.
> I'm not clear on whether _mm_mfence is meant to be a compiler memory
barrier or not.
Every authoritative reference I have found is maddeningly silent on this
point.
However, I have tried compiling x64 code with MSVC, and the instruction
ordering it produces for _mm_mfence is not the same as what it produces
for _mm_sfence. In fact, the asm produced when using _mm_sfence bears a
striking similarity to what you get with just _WriteBarrier (minus the
sfence instruction, of course), and _mm_mfence looks like _ReadWriteBarrier.
While I'm not prepared to call this conclusive evidence, it is becoming
suspicious.
And apparently I'm not the only person who thinks there is a problem
here
(http://doxygen.reactos.org/dd/dcb/intrin__x86_8h_a0dee6d755a43d9f9d8072d6202b487db.html#a0dee6d755a43d9f9d8072d6202b487db).
I was concerned about using 2 statements and hoping the compiler didn't
re-order any code around them. I'm not convinced that 3 statements
makes me feel any better.
dw
next prev parent reply other threads:[~2013-06-05 2:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-04 22:58 dw
2013-06-04 23:52 ` Ian Lance Taylor
2013-06-05 2:45 ` dw [this message]
2013-06-05 4:30 ` Ian Lance Taylor
2013-06-12 8:15 ` dw
2013-06-12 19:01 ` Ian Lance Taylor
2013-06-13 2:55 ` dw
2013-06-13 3:01 ` Chung-Ju Wu
2013-06-13 3:25 ` Ian Lance Taylor
2013-06-13 3:44 ` dw
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