From: Florian Weimer <fweimer@redhat.com>
To: Satish Vasudeva via Gcc-help <gcc-help@gcc.gnu.org>
Cc: Satish Vasudeva <satish.vasudeva@cohesity.com>
Subject: Re: Libatomic 16B
Date: Fri, 25 Feb 2022 14:53:42 +0100 [thread overview]
Message-ID: <878rtzvyqh.fsf@oldenburg.str.redhat.com> (raw)
In-Reply-To: <CABp-VvKtwepyq0388-0gXtoLQGfwKkoHsh1pvWcw4r_Ng8iihg@mail.gmail.com> (Satish Vasudeva via Gcc-help's message of "Thu, 24 Feb 2022 08:42:56 -0800")
* Satish Vasudeva via Gcc-help:
> I looked into this further. Seems like libat_load_16_i1 is implementing the
> load 16B as "*lock* *cmpxchg16b* (%*rdi*)"
> This is assuming that the CPU doesn't support 16B loads in a single
> transaction. How can I compile libatomics to use intrinsics for load 16B
> instead of LOCK cmpxchg?
As far as I know, it's the only reliable way to implement a 16B load on
x86-64. The Intel SDM explicitly says this:
| An x87 instruction or an SSE instructions that accesses data larger
| than a quadword may be implemented using multiple memory accesses.
(Section 8.1.1 in Volume 3A in my copy.)
I wish we had a plain 128-bit atomic load instruction, but we don't.
Thanks,
Florian
next prev parent reply other threads:[~2022-02-25 13:53 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-23 16:42 Satish Vasudeva
2022-02-24 16:42 ` Satish Vasudeva
2022-02-25 13:53 ` Florian Weimer [this message]
2022-02-24 19:09 ` Xi Ruoyao
2022-02-24 19:35 ` Satish Vasudeva
2022-02-24 20:05 ` Xi Ruoyao
2022-02-24 20:13 ` Segher Boessenkool
2022-02-24 20:38 ` Satish Vasudeva
2022-02-25 8:35 ` Stefan Ring
2022-02-25 8:48 ` Xi Ruoyao
2022-02-25 14:01 ` Florian Weimer
2022-02-25 14:10 ` Alexander Monakov
2022-02-25 14:16 ` Xi Ruoyao
2022-02-25 14:25 ` Xi Ruoyao
2022-02-25 17:05 ` Satish Vasudeva
2022-02-25 17:16 ` Xi Ruoyao
2022-02-25 17:25 ` Satish Vasudeva
2022-03-02 0:16 ` Satish Vasudeva
2022-03-02 5:55 ` Florian Weimer
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