From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4784 invoked by alias); 21 Oct 2011 20:16:44 -0000 Received: (qmail 4750 invoked by uid 22791); 21 Oct 2011 20:16:41 -0000 X-SWARE-Spam-Status: No, hits=-0.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-wy0-f175.google.com (HELO mail-wy0-f175.google.com) (74.125.82.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 21 Oct 2011 20:16:29 +0000 Received: by wyg19 with SMTP id 19so4843022wyg.20 for ; Fri, 21 Oct 2011 13:16:28 -0700 (PDT) MIME-Version: 1.0 Received: by 10.227.58.84 with SMTP id f20mr7066172wbh.9.1319228187911; Fri, 21 Oct 2011 13:16:27 -0700 (PDT) Received: by 10.180.86.228 with HTTP; Fri, 21 Oct 2011 13:16:27 -0700 (PDT) Date: Fri, 21 Oct 2011 20:16:00 -0000 Message-ID: Subject: Adding custom instructions to bcc From: Joshua Weber To: gcc-help@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Mailing-List: contact gcc-help-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-help-owner@gcc.gnu.org X-SW-Source: 2011-10/txt/msg00193.txt.bz2 I am looking to be able to add custom instructions to the gcc/gas compiler. I have already written a full microprocessor simulator that simulates execution of all machine code. I am looking to extend the instruction set of the microprocessor to support new custom instructions. I would ideally like to be able to simply place custom instructions in C code using asm blocks. I would even be happy with coding in machine code directly (hexadecimal definitions) in asm blocks. I have been attempting to read and understand the internals of both gcc and the binutils (gas). I still feel unclear if I need to modify gcc at all. Would the simple addition of the new opcodes to the binutils/opcodes/-opc.c file be sufficient to support the additional custom instructions? Any help in this regard would be greatly appreciated. I have failed to identify many online resources for this, even though there seems to be a degree of interest in it. It is very common within the SoC and FPGA microprocessor world for the extension of the ISA to include new instructions, and yet there is very little existing documentation on this subject. Thanks, Joshua Weber