Re: Complex half-word operations

[Ayonam Ray <ayonam@gmail.com>]

On 18 October 2011 22:38, Ian Lance Taylor <iant@google.com> wrote:
> On Tue, Oct 18, 2011 at 9:30 AM, Ayonam Ray <ayonam@gmail.com> wrote:
>> I'm trying to define a complex half word operation (add:CHI) using the
>> following RTL:
>>
>> (define_insn "addchi3"
>>   [(set (match_operand:CHI 0 "register_operand" "=r")
>>         (plus:CHI (match_operand:CHI 1 "register_operand" "r")
>>                   (match_operand:CHI 2 "register_operand" "r")))]
>>   ""
>>   "cmplxadd\t%1, %2, %0"
>>   [(set_attr "type" "complex")
>>    (set_attr "slot" "s1")
>>    (set_attr "predicable" "no")
>>    (set_attr "length" "4")])
>>
>> This architecture can perform arithmetic operations on "complex short"
>> data by packing the real and imaginary parts into two half words of a
>> 32-bit general register.
>>
>> However, the instruction matcher doesn't seem to generate this RTL at
>> all.  It splits the operation into two half word additions.  I have
>> handled the CHImode in the macros HARD_REGNO_NREGS, and
>> HARD_REGNO_MODE_OK.  How do we tell GCC that the real and imaginary
>> parts are actually packed into a single register?  I tried defining
>> two RTLs to pack and unpack the two parts using the concat:CHI
>> operation.
>
> I don't think the gcc middle-end has any support for machines which provide
> special handling for complex int.  I think the middle-end always breaks up
> complex int operations into pairs of int operations.  So to make this work you
> would probably have to add that support.
>
> Ian
>

Thanks Ian for the reply.  Can you please point me to the files in the
middle-end where I may find the relevant code?