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Date: Tue, 18 Oct 2011 17:20:00 -0000
Message-ID: <CA+V5N8=Uhhu1jNnyBqgV_VxrpXpFHV9Ze9UjTLF4-TvOWphLow@mail.gmail.com>
Subject: Re: Complex half-word operations
From: Ayonam Ray <ayonam@gmail.com>
To: Ian Lance Taylor <iant@google.com>
Cc: gcc-help@gcc.gnu.org
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On 18 October 2011 22:38, Ian Lance Taylor <iant@google.com> wrote:
> On Tue, Oct 18, 2011 at 9:30 AM, Ayonam Ray <ayonam@gmail.com> wrote:
>> I'm trying to define a complex half word operation (add:CHI) using the
>> following RTL:
>>
>> (define_insn "addchi3"
>> =A0 [(set (match_operand:CHI 0 "register_operand" "=3Dr")
>> =A0=A0=A0=A0=A0=A0=A0 (plus:CHI (match_operand:CHI 1 "register_operand" =
"r")
>> =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_operand:CHI 2=
 "register_operand" "r")))]
>> =A0 ""
>> =A0 "cmplxadd\t%1, %2, %0"
>> =A0 [(set_attr "type" "complex")
>> =A0=A0 (set_attr "slot" "s1")
>> =A0=A0 (set_attr "predicable" "no")
>> =A0=A0 (set_attr "length" "4")])
>>
>> This architecture can perform arithmetic operations on "complex short"
>> data by packing the real and imaginary parts into two half words of a
>> 32-bit general register.
>>
>> However, the instruction matcher doesn't seem to generate this RTL at
>> all.=A0 It splits the operation into two half word additions.=A0 I have
>> handled the CHImode in the macros HARD_REGNO_NREGS, and
>> HARD_REGNO_MODE_OK.=A0 How do we tell GCC that the real and imaginary
>> parts are actually packed into a single register?=A0 I tried defining
>> two RTLs to pack and unpack the two parts using the concat:CHI
>> operation.
>
> I don't think the gcc middle-end has any support for machines which provi=
de
> special handling for complex int. =A0I think the middle-end always breaks=
 up
> complex int operations into pairs of int operations. =A0So to make this w=
ork you
> would probably have to add that support.
>
> Ian
>

Thanks Ian for the reply.  Can you please point me to the files in the
middle-end where I may find the relevant code?