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From: Reshabh K Sharma <reshabh@cs.washington.edu>
Date: Wed, 26 Jan 2022 17:20:35 -0800
Message-ID: <CAAhFPT0yhaVgT1G_9eUcB77gaTyqHL1nUQO06c5GhEaGv2nJJQ@mail.gmail.com>
Subject: Describe instructions with same reg in def and use or mutiple defs
 and attach write latency
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Hello everyone,

I am trying to implement a post address update load instruction in our
downstream riscv backend. I want to attach write latency information to a
use register. For example, rd = new_load rs1 rs2, I want to attach separate
write latency information to both rd and rs1.

I am unable to find how to describe instructions that have an operand as
both def and use, and later attach write latency information for the
instruction scheduler to work properly.

It will also be very helpful if you can point me to the implementation of
similar instructions in other backends, for example, LBZU in PowerPC, ARM's
LWD post/pre address update versions and ARM's neon simd load with update.

Many thanks,
Reshabh